GS88018BT-300I GSI [GSI Technology], GS88018BT-300I Datasheet - Page 7

• Manufacturer Part Number: GS88018BT-300I
• Description: 512K x 18, 256K x 32, 256K x 36 9Mb Sync Burst SRAMs
• Manufacturer: GSI [GSI Technology]

Mode Pin Functions
Note:
There is a pull-up device onthe FT pin and a pull-down device on the ZZ pin, so those this input pins can be unconnected and the chip will
operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
Rev: 1.04 2/2005
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
2nd address
1st address
3rd address
4th address
FLXDrive Output Impedance Control
Output Register Control
Power Down Control
Burst Order Control
Mode Name
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
01
10
11
00
10
00
01
11
11
00
01
10
Pin Name
7/24
LBO
ZQ
ZZ
FT
Interleaved Burst Sequence
Note:
The burst counter wraps to initial state on the 5th clock.
2nd address
1st address
3rd address
4th address
H or NC
H or NC
L or NC
State
H
H
L
L
L
GS88018/32/36BT-333/300/250/200/150
A[1:0] A[1:0] A[1:0] A[1:0]
00
01
10
11
High Drive (Low Impedance)
Low Drive (High Impedance)
01
00
11
10
Standby, I
Interleaved Burst
Flow Through
Linear Burst
Function
Pipeline
Active
10
00
01
11
DD
© 2002, GSI Technology
= I
SB
11
10
01
00
BPR 1999.05.18