MT55L256L36P MICRON [Micron Technology], MT55L256L36P Datasheet - Page 13

• Manufacturer Part Number: MT55L256L36P
• Description: 8Mb ZBT SRAM
• Manufacturer: MICRON [Micron Technology]

BGA PIN DESCRIPTIONS
8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM
MT55L512L18P_2.p65 – Rev. 6/01
2T, 3T, 5T, 6T
2A, 3A, 5A,
6A, 3B, 5B,
2C, 3C, 5C,
6C, 2R, 6R,
x 1 8
4 M
4 N
3 G
4 H
4K
6 B
2 B
4P
5 L
4E
7T
–
–
2A, 2C, 2R,
3A, 3B, 3C,
3T, 4T, 5A,
5B, 5C, 5T,
6A, 6C, 6R
x32/x36
4 M
4 N
5 G
3 G
4 H
4K
6 B
2 B
4P
5 L
3 L
4E
7T
S Y M B O L T Y P E
BWb#
BWd#
BWa#
BWc#
R/W#
CKE#
CE2#
SA0
SA1
CLK
CE#
CE2
S A
ZZ
Input Synchronous Address Inputs: These inputs are registered and
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Synchronous Clock Enable: This active LOW input permits CLK to
Input Read/Write: This input determines the cycle type when ADV/
Input Clock: This signal registers the address, data, chip enable, byte write
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to enable
(continued on next page)
must meet the setup and hold times around the rising edge
of CLK.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.
For the x32 and x36 versions, BWa# controls DQa’s and DQPa;
BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd. Parity is only available on the x18
and x36 versions.
propagate throughout the device. When CKE# is HIGH, the
device ignores the CK input and effectively internally extends
the previous CLK cycle. This input must meet the setup and
hold times around the rising edge of CLK.
LD# is lOW and is the only means for determining READs and
WRITEs. READ cycles may not be converted into WRITEs (and
vice versa) other than by loading a new address. A LOW on this
pin permits BYTE WRITE operations must meet the setup and
hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
the device. CE# is sampled only when a new external address is
loaded.
the device and is sampled only when a new external address is
loaded.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
the device and is sampled only when a new external address is
loaded.
13
8Mb: 512K x 18, 256K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D E S C R I P T I O N
PIPELINED ZBT SRAM
©2001, Micron Technology, Inc.