HYS64T128020HU-5-B QIMONDA [Qimonda AG], HYS64T128020HU-5-B Datasheet - Page 18

• Manufacturer Part Number: HYS64T128020HU-5-B
• Description: 240-Pin unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

3.3
This chapter describes the AC Characteristics.
3.3.1
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(
Speed Grade Definition for:
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
3) Inputs are not recognized as valid until
4) The output timing reference voltage level is
5)
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Speed Grade
QAG Sort Name
CAS-RCD-RP latencies
Parameter
Clock Frequency
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
input reference level is the crosspoint when in differential strobe mode.
t
RAS.MAX
is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x
Timing Characteristics
Speed Grade Definitions
@ CL = 3
@ CL = 4
@ CL = 5
DDR2–800(Table
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
V
REF
V
Symbol
t
t
t
stabilizes. During the period before
CK
CK
CK
TT
Symbol
t
t
t
t
t
t
t
t
.
CK
CK
CK
CK
RAS
RC
RCD
RP
12),
DDR2–667(Table
DDR2–667C
–3
4–4–4
Min.
5
3
3
DDR2–800D
–25F
5–5–5
Min.
5
3.75
2.5
2.5
45
57.5
12.5
12.5
18
Speed Grade Definition Speed Bins for DDR2–800
Speed Grade Definition Speed Bins for DDR2–667
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
Max.
8
8
8
13),
Max.
8
8
8
8
70000
—
—
—
DDR2–533C(Table
V
REF
stabilizes, CKE = 0.2 x
DDR2–667D
–3S
5–5–5
Min.
5
3.75
3
DDR2–800E
–2.5
6–6–6
Min.
5
3.75
3
2.5
45
60
15
15
Unbuffered DDR2 SDRAM Module
Max.
8
8
8
Max.
8
8
8
8
70000
—
—
—
14) and
t
CK
V
= 5ns with
DDQ
DDR2–400B(Table
Unit
t
—
ns
ns
ns
CK
Internet Data Sheet
Unit
t
—
ns
ns
ns
ns
ns
ns
ns
ns
CK
is recognized as low.
TABLE 12
TABLE 13
t
RAS
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
Note
1)2)3)4)
1)2)3)4)
1)2)3)4)
= 40ns).
t
REFI
15)
.