M391T6553BGZ0-CD5/CC SAMSUNG [Samsung semiconductor], M391T6553BGZ0-CD5/CC Datasheet - Page 18

• Manufacturer Part Number: M391T6553BGZ0-CD5/CC
• Description: 240pin Unbuffered Module based on 512Mb B-die 64/72-bit Non-ECC/ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

256MB, 512MB, 1GB Unbuffered DIMMs
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Activate Window for 1KB page size products
Four Activate Window for 2KB page size products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE asynchronously drops LOW
Parameter
tWPST
tWPRE
tIH
tIS
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tDAL
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
t
t
t
t
t
t
t
tANPD
tAXPD
tOIT
tDelay
CKE
AOND
AON
AONPD
AOFD
AOF
AOFPD
Symbol
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tRFC + 10
tWR+tRP
tAC(min)
tAC(min)
6 - AL
min
37.5
375
250
200
0.4
0.35
0.9
0.4
7.5
7.5
7.5
2.5
10
50
15
3
2
2
2
3
8
0
2
DDR2-533
2tCK+tAC(m
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2.5tCK+
ax)+1
max
0.6
1.1
0.6
2.5
12
x
x
x
x
2
x
x
x
x
x
x
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tRFC + 10
tWR+tRP
tAC(min)
tAC(min)
6 - AL
min
37.5
0.35
475
350
200
0.4
0.9
0.4
7.5
7.5
2.5
10
50
15
10
3
2
2
2
3
8
0
2
DDR2-400
Rev. 1.5 Aug. 2005
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2tCK+tAC
DDR2 SDRAM
(max)+1
2.5tCK+
max
0.6
1.1
0.6
2.5
12
x
x
x
2
x
x
x
x
x
x
x
tCK
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes