M378B2873GB0 SAMSUNG [Samsung semiconductor], M378B2873GB0 Datasheet - Page 18

• Manufacturer Part Number: M378B2873GB0
• Description: 240pin Unbuffered DIMM based on 1Gb G-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
12.3.3 Single-ended Requirements for Differential Signals
Each individual component of a differential signal (CK, DQS, CK, DQS) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach V
half-cycle.
DQS, DQS have to reach V
ing a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if V
signals, then these ac-levels apply also for the single-ended signals CK and CK .
Note that while ADD/CMD and DQ signal requirements are with respect to V
with respect to V
ended components of differential signals the requirement to reach V
mode characteristics of these signals.
[ Table 5 ] Single ended levels for CK, DQS, CK, DQS
NOTE :
1. For CK, CK use V
2. V
3. These values are not defined, however the single-ended signals CK, CK, DQS, DQS need to be within the respective limits (V
reduced level applies also here
nals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification"
IH
(AC)/V
Symbol
V
V
SEH
SEL
IL
(AC) for DQs is based on V
DD
IH
/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-
/V
IL
Single-ended high-level for CK, CK
Single-ended high-level for strobes
(AC) of ADD/CMD; for strobes (DQS, DQS) use V
Single-ended low-level for strobes
Single-ended low-level for CK, CK
V
DD
SEH
V
/2 or V
V
DD
SS
min / V
V
V
SEL
or V
SEH
or V
Parameter
DDQ
REFDQ
max
SEL
DDQ
SSQ
min
/2
max (approximately the ac-levels ( V
; V
SEH
IH
(AC)/V
min / V
Figure 4. Single-ended requirement for differential signals
IL
(AC) for ADD/CMD is based on V
SEL
max (approximately equal to the ac-levels ( V
datasheet
IH
/V
V
SEL
IL
SEH
(AC) of DQs.
(V
(V
max, V
DD
DD
NOTE 3
NOTE 3
- 18 -
REF
/2)+0.175
/2)+0.175
Min
IH
(AC) / V
SEH
, the single-ended components of differential signals have a requirement
DDR3-800/1066/1333/1600/1866
REFCA
min has no bearing on timing, but adds a restriction on the common
IL
; if a reduced ac-high or ac-low level is used for a signal group, then the
(AC) ) for DQ signals) in every half-cycle proceeding and follow-
IH
V
IH
(AC) / V
SEL
150(AC)/V
(V
(V
DD
DD
NOTE 3
NOTE 3
IL
IH
Max
/2)-0.175
/2)-0.175
(AC) ) for ADD/CMD signals) in every
(DC) max, V
CK or DQS
IL
150(AC) is used for ADD/CMD
DDR3 SDRAM
time
IL
(DC)min) for single-ended sig-
Unit
V
V
V
V
Rev. 1.2
NOTE
1, 2
1, 2
1, 2
1, 2