M470T2864AZ3-CLE6/D5/CC SAMSUNG [Samsung semiconductor], M470T2864AZ3-CLE6/D5/CC Datasheet - Page 17

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M470T2864AZ3-CLE6/D5/CC

Manufacturer Part Number
M470T2864AZ3-CLE6/D5/CC
Description
DDR2 Unbuffered SODIMM 200pin Unbuffered SODIMM based on 1Gb A-die 64-bit Non-ECC
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
SODIMM
Exit active power down to read command
Exit active power down to read command
(slow exit, lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after
CKE asynchronously drops LOW
Parameter
Symbol
tXARD
tXARDS
t
t
t
t
t
t
t
tANPD
tAXPD
tOIT
tDelay
CKE
AOND
AON
AONPD
AOFD
AOF
AOFPD
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
tIS+tCK
7 - AL
+tIH
min
2.5
3
2
3
8
0
2
DDR2-667
2.5tCK+tAC
tAC(max)+
2tCK+tAC(
tAC(max)+
17 of 20
(max)+1
max)+1
max
0.7
2.5
0.6
12
2
x
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
tIS+tCK
6 - AL
+tIH
min
2.5
3
2
3
8
0
2
DDR2-533
tAC(max)+
2tCK+tAC(
tAC(max)+
tAC(max)+
2.5tCK+
max)+1
max
2.5
0.6
12
2
1
1
x
tAC(min)+2
tAC(min)+2
tAC(min)
tAC(min)
tIS+tCK
6 - AL
+tIH
min
2.5
3
2
3
8
0
2
DDR2-400
Rev. 1.4 March 2007
DDR2 SDRAM
tAC(max)+1
tAC(max)+1
tAC(max)+
2tCK+tAC
(max)+1
2.5tCK+
max
2.5
0.6
12
2
x
Units
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
Note

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