HYS64D16001GDL-7-B INFINEON [Infineon Technologies AG], HYS64D16001GDL-7-B Datasheet - Page 20
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HYS64D16001GDL-7-B
Manufacturer Part Number
HYS64D16001GDL-7-B
Description
200-Pin Small Outline Dual-In-Line Memory Modules
Manufacturer
INFINEON [Infineon Technologies AG]
Datasheet
1.HYS64D16001GDL-7-B.pdf
(31 pages)
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate
11) For each of the terms, if not already an integer, round to the next highest integer.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 12
Parameter
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock Half Period
Clock cycle time
DQ and DM input hold time
DQ and DM input setup time
Control and Addr. input pulse width
(each input)
DQ and DM input pulse width (each
input)
Data-out high-impedance time from CK/
CK
Data-out low-impedance time from CK/
CK
Write command to 1
transition
DQS-DQ skew (DQS and associated
DQ signals)
Data hold skew factor
DQ/DQS output hold time
DQS input low (high) pulse width (write
cycle)
Data Sheet
system performance (bus turnaround) degrades accordingly.
ns, measured between
cycle time.
AC Timing - Absolute Specifications –8/–7
1.0 V/ns , slow slew rate
st
DQS latching
V
OH(ac)
and
V
OL(ac)
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
DQSCK
CH
CL
HP
CK3
CK2.5
CK2
CK1.5
DH
DS
IPW
DIPW
HZ
LZ
DQSS
DQSQ
QHS
QH
DQSL,H
.
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
Min
.
–
0.8
–
0.8
0.4
5
0.4
5
8
8
10
10
0.6 —
0.6 —
2.5 —
2.0 —
–
0.8
–
0.8
0.7
5
—
—
t
–
t
S
0.3
5
min. (
HP
QH
DDR200
20
Max.
+0.8
+0.8
0.55
0.55
12
12
12
12
+0.8
+0.8
1.25
+0.6
1.0
—
—
t
–8
CL
,
t
CH
HYS64D[1600x/32020]GDL–[5/6/7/8]–B
)
Small Outline DDR SDRAM Modules
Min.
–0.75
–0.75
0.45
0.45
7
7
7.5
—
0.5
0.5
2.2
1.75
–0.75
–0.75
0.75
—
—
t
t
0.35
HP
QHS
min. (
DDR266A
–
t
–7
CL
Max.
+0.75
+0.75
0.55
0.55
12
12
12
—
—
—
—
—
+0.75
+0.75
1.25
+0.5
0.75
—
—
t
,
CK
t
CH
is equal to the actual system clock
)
Unit Note/
ns
ns
t
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ns
ns
t
CK
CK
CK
CK
AC Characteristics
Test Condition
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
CL = 3.0
CL = 2.5
CL = 2.0
CL = 1.5
2)3)4)5)
2)3)4)5)
2)3)4)5)6)
2)3)4)5)6)
2)3)4)5)7)
2)3)4)5)7)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
V1.2, 2003-08
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
1)