M393T6450FG0-CC SAMSUNG [Samsung semiconductor], M393T6450FG0-CC Datasheet - Page 14

• Manufacturer Part Number: M393T6450FG0-CC
• Description: DDR2 Registered SDRAM MODULE 240pin Registered Module based on 256Mb F-die 72-bit ECC
• Manufacturer: SAMSUNG [Samsung semiconductor]

DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input hold time
Address and control input setup time
Read preamble
Read postamble
Active to active command period for 1KB page
size products
Active to active command period for 2KB page
size products
Four Activate Window for 1KB page size
products
Four Activate Window for 2KB page size
products
CAS to CAS command delay
Write recovery time
Auto precharge write recovery + precharge time tDAL
Internal write to read command delay
Internal read to precharge command delay
Exit self refresh to a non-read command
Exit self refresh to a read command
Exit precharge power down to any non-read
command
Exit active power down to read command
Exit active power down to read command
(Slow exit, Lower power)
CKE minimum pulse width
(high and low pulse width)
ODT turn-on delay
ODT turn-on
ODT turn-on(Power-Down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
ODT to power down entry latency
ODT power down exit latency
OCD drive mode output delay
Minimum time clocks remains ON after CKE
asynchronously drops LOW
256MB, 512MB Registered DIMMs
Parameter
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIH
tIS
tRPRE
tRPST
tRRD
tRRD
tFAW
tFAW
tCCD
tWR
tWTR
tRTP
tXSNR
tXSRD
tXP
tXARD
tXARDS
tCKE
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
tOIT
tDelay
Symbol
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tRFC + 10
tWR+tRP
tAC(min)
tAC(min)
6 - AL
min
0.35
0.35
37.5
275
200
200
0.2
0.2
0.4
0.9
0.4
7.5
7.5
2.5
10
50
7.5
15
2
2
3
2
3
8
0
2
2
DDR2-667
tAC(max)+0.7
2tCK+tAC(ma
2.5tCK+tAC(
tAC(max)+
max)+1
max
x)+1
0.6
1.1
0.6
2.5
0.6
12
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tRFC + 10
tWR+tRP
tAC(min)
tAC(min)
6 - AL
min
0.35
37.5
375
250
200
0.2
0.2
0.4
0.35
0.9
0.4
7.5
7.5
7.5
2.5
10
50
15
2
2
2
3
2
3
8
0
2
DDR2-533
2tCK+tAC(ma
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2.5tCK+
max
x)+1
0.6
1.1
0.6
2.5
12
x
x
x
x
2
x
x
x
x
x
x
x
x
x
x
tIS+tCK +tIH
tAC(min)+2
tAC(min)+2
tRFC + 10
tWR+tRP
tAC(min)
tAC(min)
6 - AL
min
0.35
37.5
0.35
475
350
200
0.2
0.2
0.4
0.9
0.4
7.5
7.5
2.5
10
50
15
10
2
2
2
3
2
3
8
0
2
DDR2-400
Rev. 1.3 Aug. 2005
DDR2 SDRAM
tAC(max)+ 0.6
tAC(max)+1
tAC(max)+1
2tCK+tAC
(max)+1
2.5tCK+
max
0.6
1.1
0.6
2.5
12
x
x
x
2
x
x
x
x
x
x
x
x
x
x
x
tCK
Units Notes
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns