IC42S32400-6B ICSI [Integrated Circuit Solution Inc], IC42S32400-6B Datasheet - Page 10
IC42S32400-6B
Manufacturer Part Number
IC42S32400-6B
Description
1M x 32 Bit x 4 Banks (128-MBIT) SDRAM
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
1.IC42S32400-6B.pdf
(62 pages)
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IC42S32400
IC42S32400L
10
CLK
D Q M
COMMAND
DQ’s
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank.The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS#latency.
CLK
DQM
COMMAND
CAS# latency=2
t CK2 , DQ’s
CLK
DQM
COMMAND
CAS# latency=2
: "H" or "L"
tCK2, DQs
: "H" or "L"
: "H" or "L"
tCK2, DQs
NOP
T0
T0
NOP
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
Read to Write Interval (Burst Length = 4,CAS#Latency =3)
T0
NOP
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
READ A
T1
T1
NOP
T1
NOP
READ A
NOP
T2
ACTIVAT E
T2
BANKA
T2
T3
T3
NOP
NOP
T3
NOP
DOUT A
NOP
T4
T4
READ A
NOP
T4
1 Clk Interval
Must be Hi-Z before
the Write Command
WRITEB
NOP
T5
T5
DIN B 0
WRITEA
T5
DIN A 0
WRITE B
DIN B 1
T6
DINB 0
T6
NOP
DIN A 1
NOP
T6
Integrated Circuit Solution Inc.
NOP
T7
T7
DINB 1
NOP
DIN B 2
T7
NOP
DIN A 2
NOP
NOP
T8
DINB 2
T8
DIN B 3
NOP
T8
DIN A 3
DR038-0C 02/01/2005
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