AT52BR1672-85CI ATMEL [ATMEL Corporation], AT52BR1672-85CI Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
AT52BR1672-85CI
Manufacturer Part Number
AT52BR1672-85CI
Description
16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT52BR1672-85CI.pdf
(39 pages)
128-BIT PROTECTION REGISTER: The 16-megabit Flash contains a 128-bit register that
can be used for security purposes in system design. The protection register is divided into two
64-bit blocks. The two blocks are designated as block A and block B. The data in block A is
non-changeable and is programmed at the factory with a unique number. The data in block B
is programmed by the user and can be locked out such that data in the block cannot be repro-
grammed. To program block B in the protection register, the four-bus cycle Program
Protection Register command must be used as shown in the Command Definition table on
page 9. To lock out block B, the four-bus cycle Lock Protection Register command must be
used as shown in the Command Definition table. Data bit D1 must be zero during the fourth
bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Pro-
tection Register Addressing Table” on page 10 for the address locations in the protection
register. To read the protection register, the Product ID Entry command is given followed by a
normal read operation from an address within the protection register. After reading the protec-
tion register, the Product ID Exit command must be given prior to performing any other
operation.
DATA POLLING: The Flash features Data Polling to indicate the end of a program cycle. Dur-
ing a program cycle an attempted read of the last word loaded will result in the complement of
the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all
outputs and the next cycle may begin. During a chip or sector erase operation, an attempt to
read the device will give a “0” on I/O7. Once the program or erase cycle has completed, true
data will be read from the device. Data Polling may begin at any time during the program
cycle. Please see “Status Bit Table” on page 22 for more details.
TOGGLE BIT: In addition to Data Polling, the 16-megabit Flash provides another method for
determining the end of a program or erase cycle. During a program or erase operation, suc-
cessive attempts to read data from the same memory plane will result in I/O6 toggling between
one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data
will be read. Examining the toggle bit may begin at any time during a program cycle.
An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle
bit that is available on I/O6. While a sector is erase suspended, a read or a program operation
from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on
page 22 for more details.
RDY/BUSY: For the 16-megabit Flash, an open-drain Ready/Busy output pin provides
another method of detecting the end of a program or erase operation. RDY/BUSY is actively
pulled low during the internal program and erase cycles and is released at the completion of
the cycle. The open-drain connection allows for OR-tying of several devices to the same
RDY/BUSY line.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the Flash in the following ways: (a) V
sense: if V
is below 1.8V
CC
CC
(typical), the program function is inhibited. (b) V
power-on delay: once V
has reached the
CC
CC
V
sense level, the device will automatically time out 10 ms (typical) before programming. (c)
CC
Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)
Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a pro-
gram cycle.
INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to V
+ 0.6V.
CC
OUTPUT LEVELS: For the 16-megabit Flash, output high levels (V
) are equal to V
-
OH
CCQ
0.2V (not V
). For 2.7V - 3.3V output levels, V
must be tied to V
. For 1.8V - 2.2V output
CC
CCQ
CC
levels, V
must be regulated to 2.0V ± 10%, while V
must be regulated to 2.7V - 3.0V (for
CCQ
CC
minimum power).
AT52BR1672(T)/1674(T)
8
2604B–STKD–09/02