AT52BR1672-85CI ATMEL [ATMEL Corporation], AT52BR1672-85CI Datasheet - Page 27

• Manufacturer Part Number: AT52BR1672-85CI
• Description: 16-megabit Flash and 2-megabit/ 4-megabit SRAM Stack Memory
• Manufacturer: ATMEL [ATMEL Corporation]

Output Test Load
Timing Diagrams
Read Cycle 1
Read Cycle 2
Read Cycle 3
Notes:
2604B–STKD–09/02
1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
2. SOE = V
3. Transition is measured + 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
status.
standby, low for active.
(1),(4)
IL
(1)
(1)
.
,
,
(2)
(2)
DATA OUT
DATA OUT
ADDRESS
SUB, SLB
DATA OUT
ADDRESS
SUB, SLB
,
,
(4)
(4)
SCS1
SCS2
SCS1
SCS2
SOE
HIGH-Z
PREVIOUS DATA
t
CLZ
(3)
t
OH
t
BLZ
t
t
t
AA
t
OLZ
t
ACS
CLZ
AA
(3)
(3)
(3)
t
BA
t
ACS
t
OE
t
RC
t
RC
DATA VALID
DATA VALID
DATA VALID
AT52BR1672(T)/1674(T)
t
OHZ
t
BHZ
(3)
t
(3)
CHZ
t
t
CHZ
t
OH
OH
(3)
(3)
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