HI-3110 HOLTIC [Holt Integrated Circuits], HI-3110 Datasheet - Page 20

• Manufacturer Part Number: HI-3110
• Description: Avionics CAN Controller with Integrated Transceiver
• Manufacturer: HOLTIC [Holt Integrated Circuits]

BTR1 configures the CAN protocol bit timing segments in terms of time quanta (Tq) and sets the number of sampling points. This
register can be read anytime and written only in init mode (MODE<2:0> bits set to <1xx> in the CTRL0 register).
Bit Name
7
6-4 TSEG2-2:0
3-0 TSEG1-3:0
BIT TIMING REGISTER 1: BTR1
(Write, SPI Op-code 0x1A)
(Read, SPI Op-code 0xD8)
SAMP
R/W
R/W
R/W
R/W
Default Description
0
0
0
Samples per bit.
This bit configures how many samples are taken per bit.
Notes:
recommended to sample only once at higher CAN bit rates. Bit sampling occurs at the end of
Phase Seg1.
Time Segment 2 bits <2:0>.
Tseg2 = Phase Seg2 of the CAN protocol bit timing specification. Bits TSEG2-2:0 specify the
number of time quanta in Phase Seg2.
2 must be greater than SJW.
Time Segment 1 bits <3:0>.
Tseg1 = Prop Seg + Phase Seg1 of the CAN protocol bit timing specification. Bits TSEG1-3:0
specify the number of time quanta in Prop Seg + Phase Seg1. Note: Not all combinations are
valid, since Prop Seg + Phase Seg1
minimum number of Tq in a bit time shall be 8.
Notes:
this case, Tseg1 should be a minimum of 5Tq for Phase Seg2 (Tseg2) = 2Tq and SJW = 1Tq.
ARINC 825 states that there shall be only one sample per bit. Furthermore, it is
ARINC 825 states that the sample point shall not be less than 75% of the bit time. In
HOLT INTEGRATED CIRCUITS
1 =
0 =
TSEG2 bits <2:0>
TSEG1 bits <3:0>
HI-3110
MSB
7
three samples per bit.
one sample per bit.
000: Not valid
001: Tseg2 = 2 Tq clock cycles
010: Tseg2 = 3 Tq clock cycles
111: Tseg2 = 8 Tq clock cycles
0000: Not valid
0001: Tseg1 = 2 Tq clock cycles
0010: Tseg1 = 3 Tq clock cycles
0011: Tseg1 = 4 Tq clock cycles
0100: Tseg1 = 5 Tq clock cycles
1111: Tseg1 = 16 Tq clock cycles
20
6
5
³
.
etc.
.
.
.
.
4
Phase Seg 2.
Note:
3
2
Not all combinations are valid, since Phase Seg
1
LSB
0
The CAN protocol states that the