SI53152-A01AGMR Silicon Laboratories Inc, SI53152-A01AGMR Datasheet

SI53152-A01AGMR

Manufacturer Part Number

SI53152-A01AGMR

Description

Manufacturer

Silicon Laboratories Inc

Datasheet

1.SI53152-A01AGM.pdf (20 pages)

Specifications of SI53152-A01AGMR

Lead_time

Pack_quantity

2500

Comm_code

85423990

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Amily Shenzhen XNWY Technology Co., Ltd

Part Number:

SI53152-A01AGMR

Company:

H&T Electronics

Part Number:

SI53152-A01AGMR

Quantity:

7 500

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PCI-E

Features



Applications



Description

The Si53152 is a spread aware PCIe clock buffer that can source two

PCIe clocks simultaneously. The device has two hardware output enable

control inputs for enabling the respective differential outputs on the fly

while powered on along with output enable control through I

communication. In addition to the hardware control pins, I

programmability is also available to promptly achieve optimum clock

signal integrity through skew and edge rate control on true, compliment,

or both differential outputs as well as amplitude control.

Functional Block Diagram

Preliminary 0.1 1/12

PCI-Express Gen 1, Gen 2, &

Gen 3 compliant

Low power push-pull type

differential output buffers

Integrated resistors on differential

clocks

Dedicated output enable

hardware pin for each clock

Two PCI-Express buffered clocks

Network attached storage

Multi-function Printer

DIFFIN

OE [1:0]

SDATA

This information applies to a product under development. Its characteristics and specifications are subject to change without notice.

SCLK

XPRESS

Control & Memory

Control

RAM



1, G

Differential clock input

capabilities

Industrial temperature:

–40 to 85

3.3 V Power supply

24-pin QFN package

Wireless access point

Routers

C support with readback

2, & G

DIFF0

DIFF1

3 F

Patents pending

*Note: Internal 100 kohm pull-up.

OE_DIFF0*

VDD

VSS

ANOUT

Ordering Information:

Pin Assignments

S i 5 3 1 5 2

See page 17

GND

UFFER

Si53152

OE_DIFF1*

VDD

DIFF1

DIFF0

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