EM25LV010-25KGBS EMC [ELAN Microelectronics Corp], EM25LV010-25KGBS Datasheet - Page 8

• Manufacturer Part Number: EM25LV010-25KGBS
• Description: 1 Megabit (128K x 8) Serial Flash Memory
• Manufacturer: EMC [ELAN Microelectronics Corp]

Device Operation
This specification is subject to change without further notice. (11.08.2004 V1.0)
The EM25LV010 uses Instruction to initiate the memory operation functions. The
Instructions are written to the device by asserting Serial Data In (D) input while keeping Chip
Select (S#) Low and are latched on the rising edge of Serial Clock(C).
Note:
Hold Function
The Hold (HOLD#) signal allows the EM25LV010 operation to be paused while it is actively
selected with S# at low. To enter into the Hold condition, the device must be selected with
Chip Select (S#) at Low. However, setting this Hold signal Low does not terminate any Write
Status Register, Program, or Erase cycle that is currently in progress.
The Hold condition starts on the falling edge of the Hold (HOLD#) signal, provided that this
coincides with Serial Clock (C) being at Low (shown in Figure 9). The Hold condition ends on
the rising edge of the Hold (HOLD#) signal, provided that this coincides with Serial Clock (C)
being at Low as well.
If the falling edge does not coincide with Serial Clock (C) being at Low, the Hold condition will
start when Serial Clock (C) goes Low. Similarly, if Serial Clock (C) is not at Low, the Hold
condition will end when Serial Clock (C) goes to Low (this is shown in Figure 9). During the
Hold condition, the Serial Data Output (Q) is at high impedance, and the Serial Data Input (D)
& Serial Clock (C) are Don’t Care.
Normally, the device is kept selected with Chip Select (S#) driven Low for the whole duration
of the Hold condition. This is to assure that the state of the internal logic remains unchanged
from the moment it enters the Hold condition.
Read
Write
Standby
Deep Power Down Mode
Hold
Write Protect
Status Register Write
Inhibit
1
2
3
3
Operation
See Table 7 for the Instruction Set of Deep Power Down Mode.
Write Protect is enabled with the Status Register parameter BP0 and BP1 (see Table 4).
Status Register Write Inhibit will be combined with Status Register Write Disable (SRWD) and
Write Protect (W#) (see Table 6).
2
Table 5: EM25LV010 Device Operation
1
S#
V
V
V
V
V
V
V
IL
IL
IL
IL
IL
IL
IL
1 Megabit (128K x 8) Serial Flash Memory
Hold#
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
W#
V
V
V
V
V
V
V
IH
IH
IH
IH
IH
IH
IL
Address/Data In
SPECIFICATION
D
X
X
X
X
X
X
EM25LV010
Status Register out
Data Out
High Z /
High Z
High Z
High Z
High Z
High Z
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