EM25LV010-25KGBS EMC [ELAN Microelectronics Corp], EM25LV010-25KGBS Datasheet - Page 13

• Manufacturer Part Number: EM25LV010-25KGBS
• Description: 1 Megabit (128K x 8) Serial Flash Memory
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM25LV010
1 Megabit (128K x 8) Serial Flash Memory
SPECIFICATION
The Write Status Register (WRSR) instruction is entered by driving the Chip Select (S#) Low,
followed by the instruction code and the data byte on Serial Data Input (D). The instruction
sequence is shown in Figure 13. The Write Status Register (WRSR) instruction has no effect
on Bits 6, 5, 4, 1, & 0 of the Status Register. Bits 6, 5, & 4 are always read as “0.”
Chip Select (S#) must be driven High after the eighth bit of the data byte has been latched in.
Otherwise, the Write Status Register (WRSR) instruction will not execute. As soon as Chip
Select (S#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is
initiated. While the Write Status Register cycle is in progress, the Status Register may still be
read to check the value of the (BUSY) bit. The (BUSY) bit is “1” during the self-timed Write
Status Register cycle, and is “0” when it is completed. At some unspecified time before the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows user to change the values of the Block
Protect (BP1, BP0) bits, and to define the size of the area that is to be treated as read-only as
defined in Table 4. The Write Status Register (WRSR) instruction also allows the user to set
or reset the Status Register Write Disable (SRWD) bit in accordance with the Write Protect
(W#) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W#) signal
allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register
(WRSR) instruction will not be executed once the Hardware Protected Mode (HPM) is
entered.
Read Data Bytes (READ)
The Read Data instruction allows one or more data bytes to be read in sequence from the
memory. The instruction is initiated by driving the Chip Select (S#) Low. The instruction
code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0),
each bit being latched in during the rising edge of Serial Clock (C). Then the memory data at
that address is shifted out on Serial Data Output (Q) with each bit being shifted out at a
maximum frequency fR during the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 14. The first byte address can be situated at any
location. The address is automatically incremented to the next higher address after each
byte of data is shifted out. The whole memory can, therefore, be read with a single Read
Data Bytes (READ) instruction. When the highest address is reached, the address counter
rolls over to 000000h, allowing the read sequence to continue indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S#) High.
Chip Select (S#) can be driven High at any time during data output. Any Read Data Bytes
(READ) instruction executed while a Program or Write cycle is in progress, is rejected without
having any effects on the cycle that is in progress.
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This specification is subject to change without further notice. (11.08.2004 V1.0)