S71WS256PD0HFFLW0 SPANSION [SPANSION], S71WS256PD0HFFLW0 Datasheet - Page 9

• Manufacturer Part Number: S71WS256PD0HFFLW0
• Description: based MCP/POP Products
• Manufacturer: SPANSION [SPANSION]

5.
S75WS-P_00_02 September 6, 2006
Input/Output Descriptions
Table 5.1
Amax-A0
DQ15-DQ0
F-CE#
OE#
WE#
F-V
F-V
V
RFU
RDY
CLK
AVD#
F-RST#
F-WP#
F-ACC
R-CE#
R-MRS
R-V
R-UB#
R-LB#
DNU
N-CLE
N-ALE
SS
D a t a
CC
CCQ
CC
Symbol
identifies the input and output package connections provided on the device.
S h e e t
Ground
Signal
Output
Output
Power
Power
Power
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
—
—
( A d v a n c e
NOR Flash Address inputs
Flash Data input/output, shared between NOR and ORNAND
Flash; shared with IO15-IO0 for ORNAND
NOR Flash Chip-enable input #1. Asynchronous relative to CLK
for Burst Mode.
Output Enable input. Asynchronous relative to CLK for Burst
mode.
Write Enable input.
NOR Flash device power supply (1.7 V - 1.95V).
Input/Output Buffer power supply.
Ground
Reserved for Future Use
Flash ready output. Indicates the status of the Burst read. V
data valid. The Flash RDY pin is shared with the WAIT pin of the
pSRAM.
NOR Flash Clock, shared with CLK of burst-mode pSRAM. The
first rising edge of CLK in conjunction with AVD# low latches the
address input and activates burst mode operation. After the initial
word is output, subsequent rising edges of CLK increment the
internal address counter. CLK should remain low during
asynchronous access.
NOR Flash Address Valid input. Shared with AVD# of burst-mode
pSRAM. Indicates to device that the valid address is present on
the address inputs.
V
mode, causes starting address to be latched on rising edge of
CLK.
V
NOR Flash hardware reset input. V
to reading array data
NOR Flash hardware write protect input. V
and erase functions in the four outermost sectors.
NOR Flash accelerated input. At V
automatically places device in unlock bypass mode. At V
disables all program and erase functions. Should be at V
other conditions.
Chip-enable input for pSRAM
Mode Select Register (pSRAM). For Type 2 only.
pSRAM Power Supply
Upper Byte Control (pSRAM)
Lower Byte Control (pSRAM)
Do Not Use
Command Latch Enable: The CLE input signal is used to control
loading of the operation mode command into the internal
command register. The command is latched into the command
register from the I/O port on the rising edge of the WE# signal
while CE# is low and CLE is High.
Address Latch Enable: The ALE signal is used to control loading
of either address information or input data into the internal
address/data register. Address information is latched on the rising
edge of WE# if CE# is low and ALE is High.
Input data is latched if CE# is low and ALE is Low.
S75WS-P based MCP/POP Products
IL
IH
Table 5.1 Input/Output Descriptions (Sheet 1 of 2)
= device ignores address inputs
= for asynchronous mode, indicates valid address; for burst
I n f o r m a t i o n )
Description
HH
IL
= device resets and returns
, accelerates programming;
IL
= disables program
IL
IH
,
for all
OL
=
(NOR)
WS
X
X
X
X
X
X
X
X
X
X
X
X
X
X
pSRAM
X
X
X
X
X
X
X
X
X
X
X
X
X
(ORNAND)
MS
X
X
X
X
7