S71WS256PD0HFFLW0 SPANSION [SPANSION], S71WS256PD0HFFLW0 Datasheet - Page 10

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S71WS256PD0HFFLW0

Manufacturer Part Number
S71WS256PD0HFFLW0
Description
based MCP/POP Products
Manufacturer
SPANSION [SPANSION]
Datasheet
8
N-CE#
N-WE#
N-RE#
N-WP#
Symbol
Signal
Output
Type
Input
Input
Input
D a t a
Chip Enable: The device enters a low-power Standby mode when
the device is in Ready mode. The CE# signal is ignored when the
device is in a Busy state (RY/BY# = L), such as during a Page
Buffer Load or Erase operation, and will not enter Standby mode
even if the CE# input goes high. The CE# signal may be inactive
during the Page Buffer write and Page Buffer load of the array
data.
Write Enable: The WE# signal is used to control the acquisition of
data from the I/O port.
Read Enable: The RE# signal controls serial data output. Data is
available t
address counter is also incremented (Address = Address + 1) on
this falling edge.
Write Protect: The WP# signal is used to protect the device from
accidental programming or erasing. This signal is usually used for
protecting the data during the power-on/off sequence when input
signals are invalid.
S75WS-P based MCP/POP Products
Table 5.1 Input/Output Descriptions (Sheet 2 of 2)
S h e e t
REA
after the falling edge of RE#. The internal column
( A d v a n c e
Description
I n f o r m a t i o n )
S75WS-P_00_02 September 6, 2006
(NOR)
WS
pSRAM
(ORNAND)
MS
X
X
X
X

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