S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 36

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

36
Automatic Sleep Mode
RESET#: Hardware Reset Pin
requires standard access time (t
of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws ac-
tive current until the operation is completed.
I
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Note that during automatic sleep mode, OE# must be at V
the device reduces current to the stated sleep mode specification. I
Characteristics” represents the automatic sleep mode current specification.
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “1”), the reset
operation is completed within a time of t
The system can read data t
Refer to the AC Characteristic tables for RESET# parameters and to 13 for the
timing diagOutput Disable Mode
When the OE# input is at V
(except for RY/BY#) are placed in the highest Impedance state.
CC3
SS
IL
in “DC Characteristics” represents the CMOS standby current specification.
±0.3 V, the device draws CMOS standby current (I
but not within V
READY
(during Embedded Algorithms). The system can thus monitor RY/
S29PL127J/S29PL064J/S29PL032J for MCP
SS
±0.3 V, the standby current will be greater.
IH
RH
A d v a n c e
, output from the device is disabled. The output pins
after the RESET# pin returns to V
CE
) for read access when the device is in either
READY
I n f o r m a t i o n
(not during Embedded Algorithms).
CC4
). If RESET# is held
S29PL127J_064J_032J_MCP_00_A3 August 12, 2004
IH
.
CC5
IH
RP
in “DC
before
ACC
, the
+