S71PL032J SPANSION [SPANSION], S71PL032J Datasheet - Page 121

• Manufacturer Part Number: S71PL032J
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Notes:
1. High-Z and Low-Z parameters are characterized and are not 100% tested.
2. The internal write time of the memory is defined by the overlap of WE#, CE#1 = V
3. Data I/O is high impedance if OE# ≥ V
4. If Chip Enable goes Inactive simultaneously with WE# = High, the output remains in a high-impedance state.
5. During the Don’t Care period in the Data I/O waveform, the I/Os are in output state and input signals should not be applied.
August 30, 2004 pSRAM_Type04_18A0
signals must be Active to initiate a write and any of these signals can terminate a write by going Inactive. The data input set-
up and hold timing should be referenced to the edge of the signal that terminates write.
A d v a n c e
Figure 46. Write Cycle 1 (WE# Controlled)
IH
.
I n f o r m a t i o n
pSRAM Type 4
IL
, CE2 = V
IH
, B
HE
and/or B
LE
=V
IL
. All
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