ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet - Page 20

• Manufacturer Part Number: ZL50233GDC
• Description: 4 Channel Voice Echo Cancellor
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

20
Note: In order to correctly write to Control Register 1 and 2 of ECB, it is necessary to write the data twice to the register, one
ZL50233
NLPDis
AutoTD
HPFDis
Bypass
AdpDis
MuteR
PHDis
NBDis
MuteS
INJDis
Reset
Reset
Bit 7
TDis
TDis
BBM
Bit 7
PAD
immediately after another. The two writes must be separated by at least 350ns and no more than 20us.
1
0
Power-up
00
hex
Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely and are put
into Power Down mode.
presence/absence of periodic phase reversals. When low, the tone detectors will trigger only upon
the presence of a 2100 Hz tone with periodic phase reversals.
When high, the non-linear processor is disabled. When low, the non-linear processors function
normally. Useful for G.165 conformance testing.
When high, the echo canceller puts itself in Bypass mode when the tone detectors detect the
presence of 2100 Hz tone. See PHDis for qualification of 2100 Hz tones.
When low, the echo canceller algorithm will remain operational regardless of the state of the 2100
Hz tone detectors.
the offset nulling filters are active and will remove DC offsets on PCM input signals.
When high, data on Sout is muted to quiet code. When low, Sout carries active code.
When high, data on Rout is muted to quiet code. When low, Rout carries active code.
When high, tone detection is disabled. When low, tone detection is enabled. When both Echo
When high, the tone detectors will trigger upon the presence of a 2100 Hz tone regardless of the
When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.
When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths. When low,
When high, the power-up initialization is executed which presets all register bits including this bit
and clears the Adaptive Filter coefficients.
When high, the noise injection process is disabled. When low, noise injection is enabled.
When high, the Back to Back configuration is enabled. When low, the Normal configuration is
enabled. Note: Do not enable Extended-Delay and BBM configurations at the same time. Always
set both BBM bits of the two echo cancellers (Control Register 1) of the same group to the same
logic value to avoid conflict.
When high, 12dB of attenuation is inserted into the Rin to Rout path. When low, the Gains register
controls the signal levels.
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The Adaptive Filter
coefficients are set to zero and the filter adaptation is stopped. When low, output data on both
Sout and Rout is a function of the echo canceller algorithm.
When high, echo canceller adaptation is disabled. The Voice Processor cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
Control Register 1 (Echo Canceller B) Bit 0 is a reserved bit and should be written “0”.
PHDis
INJDis
Bit 6
Bit 6
Power-up 02
NLPDis
Echo Canceller B (ECB): Control Register 1
BBM
Bit 5
Bit 5
hex
Functional Description of Register Bits
Functional Description of Register Bits
ECA: Control Register 2
ECB: Control Register 2
AutoTD
Zarlink Semiconductor Inc.
Bit 4
Bit 4
PAD
Bypass
NBDis
Bit 3
Bit 3
R/W Address: 20
HPFDis
AdpDis
Bit 2
Bit 2
hex
+ Base Address
01
21
MuteS
Bit 1
Bit 1
hex
hex
1
R/W Address:
R/W Address:
+ Base Address
+ Base Address
Data Sheet
MuteR
Bit 0
Bit 0
0