ZL50031QEG1 ZARLINK [Zarlink Semiconductor Inc], ZL50031QEG1 Datasheet - Page 39
ZL50031QEG1
Manufacturer Part Number
ZL50031QEG1
Description
Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50031QEG1.pdf
(74 pages)
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Note 1: n denotes an LSTi stream number from 0 to 15.
(See Note 1)
LIDn4-0
Name
No clock period shift (Default)
+ 1
+ 1
+ 1
+ 7
+
+
+
+ 1 data rate clock period
+ 2 data rate clock period
1/4
1/2
3/4
Local Input Bit Delay
1/4
1/2
3/4
3/4
data rate clock period
data rate clock period
data rate clock period
data rate clock period
data rate clock period
data rate clock period
data rate clock period
Table 11 - Local Input Bit Delay Registers (LIDR0 to LIDR5) Bits
Local Input Delay Bits 4 - 0: These five bits define how long the serial interface receiver
takes to recognize and to store bit 0 from the LSTi
The input delay can be selected to +7 3/4 data rate clock periods from the frame
boundary.
..........
Table 12 - Local Input Bit Delay Programming
Zarlink Semiconductor Inc.
ZL50031
LIDn4
39
0
0
0
0
0
0
0
0
0
1
Description
LIDn3
Corresponding Delay Bits
0
0
0
0
0
0
0
0
1
1
n
input pins: i.e., to start a new frame.
...........
LIDn2
0
0
0
0
1
1
1
1
0
1
LIDn1
0
0
1
1
0
0
1
1
0
1
Data Sheet
LIDn0
0
1
0
1
0
1
0
1
0
1
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