AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 40

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

SWITCHING CHARACTERISTICS (continued)
Notes:
1. Not shown in the timing diagrams, specifies the minimum bus cycle for a single DMA data transfer. Tested by functional data
2. Applicable parameters associated with Receive circuit are tested at t
3. Not tested.
4. CSR0 write access time (t
5. It is guaranteed that no wait states will be added by the C-LANCE if either parameter #57 or #70 is met.
6. Parameter is for design reference only.
7. Reset must be asserted for at least two rising and two falling edges of TCLK for the device to be reset. If reset is deasserted
40
No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
pattern.
(TCLK Period).
before TCLK starts, the device behavior is undefined.
AMD
Parameter
Symbol Parameter Description
t
t
t
t
t
t
t
t
t
ARYD
SRDS
RDYH
SRYH
t
t
t
t
t
t
t
RENH
t
t
t
CALE
t
SR01
SR02
SRH
CCA
RCS
CDH
HCS
CSR
SAH
SAS
SRS
CHL
CAV
CDL
ADR Hold Time After the Rising Edge of
DAS (Bus Slave)
ADR Setup Time to the Falling Edge of
DAS (Bus Slave)
Delay from the Falling Edge of ALE to the
Falling Edge of READY to insure a
Minimum Bus Cycle Time (600 ns)
Data Setup Time to the Falling Edge of
READY (Bus Slave Read)
READY Hold Time After the Rising Edge of
DAS (Bus Master)
READY Driver Turn On After the Falling
Edge of DAS (Bus Slave)
READY Driver Turn On After the Falling
Edge of DAS (Bus Slave)
READY Hold Time After the Rising Edge
of DAS (Bus Slave)
READ Hold Time After the Rising Edge of
DAS (Bus Slave)
READ Setup Time to the Falling Edge of
DAS (Bus Slave)
TCLK Rising Edge to HOLD LOW or High
Delay
TCLK to Address Valid
TCLK Rising Edge to Control Signals Active
TCLK Falling Edge to ALE LOW
TCLK Falling Edge to DAS Falling Edge
Ready Setup Time to TCLK Falling Edge
TCLK Rising Edge to DAS HIGH
HLDA Setup to TCLK Falling Edge
RENA Hold Time After the Rising Edge of
RCLK
CS recovery time between deassertion
of CS or HOLD and assertion of CS
SR01
) when STOP bit is being set can be as long as 12t
P R E L I M I N A R Y
Am79C90
(CSR0, CSR3, RAP)
Conditions
(Notes 4, 6)
(CSR1, 2)
(Note 5)
(Note 6)
(Note 5)
Test
RCT
(RCLK Period) = 100 ns, t
TCT
t
TCT
.
Min
75
0
0
0
0
0
0
0
0
0
+60
14t
6t
Typ
TCT
TCT
TCT
= 100 ns
Max
100
80
35
95
75
90
90
90
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns