AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 20

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

MERR
CERR
Register Address Port (RAP)
Bit
15:02
01:00
Control and Status Register Definition
Control and Status Register 0 (CSR0)
BABL
15
20
IDON
MISS
RINT
Bit
TINT
ERR
The C-LANCE updates CSR
vious and present value of CSR
15
AMD
CSR(1:0)
Name
Name
RES
ERR
Description
Reserved. Read as zeroes. Write as
zeroes.
CSR address select. READ/WRITE.
Selects the CSR to be accessed
through the RDP. RAP is cleared by
Bus RESET.
Description
ERROR summary is set by the
“ORing” of BABL, CERR, MISS and
MERR. ERR remains set as long as
any of the error flags are true.
ERR is read only; writing it has no ef-
fect. It is cleared by Bus RESET, set-
ting the STOP bit, or clearing the
individual error flags.
CSR(1 :0)
00
01
10
11
0
by logical “ORing” the pre-
0.
CSR
CSR
CSR
CSR
CSR
17881B-15
17881B-14
P R E L I M I N A R Y
CSR 1:0
RES
0
1
2
3
0
TDMD
TXON
INIT
STRT
STOP
RXON
INEA
INTR
Am79C90
Bit
14
13
12
CERR
Name
BABL
MISS
Description
BABBLE is a transmitter timeout er-
ror. It indicates that the transmitter
has been on the channel longer than
the time required to send the maxi-
mum length packet.
BABL is a flag which indicates ex-
cessive length in the transmit buffer.
It will be set after 1519 bytes have
been transmitted, excluding pream-
ble and start frame delimiter; the
C-LANCE will continue to transmit
until the whole packet is transmitted
or until there is a failure before the
whole packet is transmitted. When
BABL error occurs, an interrupt will
be generated if INEA = 1.
BABL is READ/CLEAR ONLY and is
set by the C-LANCE, and cleared by
writing a “1” into the bit. Writing a ”0”
has no effect. It is cleared by RESET
or by setting the STOP bit.
COLLISION ERROR indicates that
the collision input to the C-LANCE
was not asserted during the trans-
mission, nor within 4.0 s after the
transmit completed. The collision af-
ter transmission is a transceiver test
feature. This function is also known
as heartbeat or SQE (Signal Quality
Error) test.
CERR is READ/CLEAR ONLY and
is set by the C-LANCE and cleared
by writing a “1” into the bit. Writing a
“0” has no effect. It is cleared by RE-
SET or by setting the STOP bit.
CERR error will not cause an inter-
rupt to occur (INTR = 0).
MISSED PACKET is set when the
receiver loses a packet because it
does not own any receive buffer, in-
dicating loss of data.
FIFO overflow is not reported be-
cause there is no receive ring entry
in which to write status.
When MISS is set, an interrupt will
be generated if INEA = 1.
MISS is READ/CLEAR ONLY, and is
set by the C-LANCE and cleared by
writing a “1” into the bit. Writing a “0”
has no effect. It is cleared by RESET
or by setting the STOP bit.