AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 32

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

127
C-LANCE
Notes:
1. W, X, Y, Z are the packets queued for transmission.
2. A, B, C, D are the packets received by the C-LANCE.
C-LANCE DMA Transfer
(Bus Master Mode)
There are two types of DMA Transfers with the
C-LANCE:
Burst Mode DMA
Burst DMA is used for Transmission or Reception of the
Packets, (Read/Write from/to Memory).
The Burst Transfers are 8 consecutive word reads
(transmit) or writes (receive) that are done in a single
bus arbitration cycle. In other words, once the C-LANCE
receives the bus acknowledge, (HLDA = LOW), it will do
8 word transfers (8 DMA cycle, min. at 600 ns per cycle)
without releasing the bus request signal (HOLD =
LOW). If there are more than 16 bytes empty in the
Transmit FIFO, in transmit mode, or at least 16 bytes of
data, in the Receive FIFO in receive mode, when the
C-LANCE releases the bus (HOLD deasserted), the
C-LANCE will request the bus again within 700 ns
32
127
Figure 8-2. Buffer Management Descriptor Rings
Burst mode DMA
Single word DMA
0
AMD
0
W
Figure 8-1. Data Chaining (Transmit)
Output
Packet
7
7
1
Transmit
1
X
Y
6
2
6
2
(Note
1)
Z
5
3
CPU
5
3
4
4
CPU
127
0
A
A
1
B
Receive
B
C
A
B
C
17881B-33
17881B-34
5
P R E L I M I N A R Y
2
(Note
2)
C-LANCE
C
D
Am79C90
4
3
(HOLD dwell time). Burst DMAs are always 8 transfer
cycles unless there are fewer than 8 words left to be
transferred to/from the Transmit/Receive FIFO, or if
there are fewer than 8 words left to be transferred to/
from the RX/TX buffer. Transmit DMAs may be shorter
than 8 words if a collision is detected during the DMA.
Single Word DMA Transfer
The C-LANCE initiates single word DMA transfers to ac-
cess the transmit and receive rings or the initialization
block. The C-LANCE will not initiate any burst DMA
transfers while reading the initialization block. The
C-LANCE will not initiate any burst DMA transfers be-
tween the time that it discovers ownership of a descrip-
tor and the time that it reads the buffer pointer and buffer
byte count entries of that descriptor.
FIFO Operation
The dual FIFOs provide temporary buffer storage for
data being transferred between the parallel bus l/O pins
and serial I/O pins. The capacity of the Transmit FIFO is
48 bytes and the Receive FIFO is 64 bytes.
Transmit
Data is loaded into the Transmit FIFO under internal
microprogram control. The Transmit FIFO has to have
more than 16 bytes empty before the C-LANCE re-
quests the bus (HOLD is asserted). The C-LANCE will
start sending the preamble (if the line is idle) as soon as
the first byte is loaded to the Transmit FIFO from
memory.
Receive
Data is loaded into the Receive FIFO from the serial in-
put shift register during reception. Data leaves the Re-
ceive FIFO under microprogram control. The C-LANCE
microcode will wait until there are at least 16 bytes of
data in the Receive FIFO before initiating a DMA burst
transfer. Preamble and Start Frame Delimiter (SFD) are
not loaded into the Receive FIFO.
FIFOs – Memory Byte Alignment
Memory buffers may begin and end on arbitrary byte
boundaries. Parallel data is byte aligned between the
Transmit
(DAL0–DAL15). Byte alignment can be reversed by set-
ting the Byte Swap (BSWP) bit in CSR3.
TRANSMISSION – WORD READ FROM EVEN MEM-
ORY ADDRESS
BSWP=0:
BSWP=1:
TRANSMISSION – BYTE READ FROM EVEN
MEMORY ADDRESS
or
FIFO BYTE n
FIFO BYTE n + 1 gets DAL <15:08>
FIFO BYTE n
FIFO BYTE n + 1 gets DAL <07:00>
Receive
FIFO
gets DAL <07:00>
gets DAL <15:08>
and
DAL
lines