ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 4

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
Ball # BGA
K17
D17
D16
B17
T11
T10
J17
G2
G1
H2
E2
F2
F1
E1
R1
P1
K2
L2
E3DS3/OC3
C34-C44
E3/DS3
C155N
JA77P
JA77N
C155P
Name
C1.5o
C16o
C19o
RefIn
F16o
C2o
C4o
C6o
C8o
F0o
F8o
JA 77.76 MHz Clock (LVPECL Output). This differential output provides a low
jitter 77.76 MHz clock.
Frame Pulse ST-BUS 2.048 Mbps (Output). This is an 8 kHz, 244 ns, active low
framing pulse, which marks the beginning of a ST-BUS frame. This is typically used
for ST-BUS operation at 2.048 Mbps and 4.096 Mbps.
Frame Pulse ST-BUS/GCI 8.192 Mbps (Output). This is an 8 kHz, 122 ns, active
low framing pulse, which marks the beginning of a ST-BUS/GCI frame. This is
typically used for ST-BUS/GCI operation at 8.192 Mbps.
Frame Pulse ST-BUS 8.192 Mbps (Output). This is an 8 kHz, 61 ns, active low
framing pulse, which marks the beginning of a ST-BUS frame. This is typically used
for ST-BUS operation at 8.192 Mbps.
Clock 1.544 MHz (Output). This output provides a 1.544 MHz DS1 rate clock.
Clock 2.048 MHz (Output). This output provides a 2.048 MHz E1 rate clock, which
can be used for ST-BUS operation at 2.048 Mbps.
Clock 4.096 MHz (Output). This clock is used for ST-BUS operation at
4.096 Mbps.
Clock 6.312 MHz (Output). This output provides a 6.312 MHz DS2 rate clock.
Clock 8.192 MHz (Output). This clock is used for ST-BUS operation at
8.192 Mbps.
Clock 16.384 MHz (Output). This clock is used for ST-BUS operation at
16.384 Mbps.
Clock 19.44 MHz (Output). This output provides a 19.44 MHz clock, which must
be connected to the RefIn input.
APLL Reference (Input). This is the input reference of the APLL circuitry and must
be linked directly to the C19o output. (Note 1)
Clock 34.368 MHz / Clock 44.736 MHz (Output). This clock can provide several
frequency outputs, depending on the status of the E3/DS3 and E3DS3/OC3 input
pins, see Figure 4 for details.
Clock 155.52 MHz (LVDS Output). Differential outputs for a 155.52 MHz clock.
These outputs are enabled by applying logic 0 to E3DS3/OC3 input or can be
switched into high impedance state by applying logic 1 to E3DS3/OC3 input.
E3DS3 or OC3 Selection Input. Logic 0 on this pin enables the C155P/N outputs
and enables the C34/C44 output to provide an 8.592 MHz or 11.184 MHz clock.
Logic 1 at this input sets the C155P/N clock outputs into high impedance and
enables C34/C44 outputs to provide 34.368 MHz or 44.736 MHz clock.
E3 or DS3 Selection (Input). When the E3DS3/OC3 pin is set to logic 1, a logic 0
on E3/DS3 pin selects a 44.736 MHz clock on C34/C44 output and logic 1 selects
34.368 MHz clock. When the E3DS3/OC3 pin is set to logic 0, a logic 0 on E3/DS3
pin selects 11.184 MHz clock on C34/C44 output and logic 1 selects 8.592 MHz
clock.
Zarlink Semiconductor Inc.
ZL30461
4
Description
Data Sheet