ZL30461MGG ZARLINK [Zarlink Semiconductor Inc], ZL30461MGG Datasheet - Page 3

• Manufacturer Part Number: ZL30461MGG
• Description: COMPACT STRATUM 3 TIMING MODULE
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Pin Description (continued)
Ball # BGA
A10
B10
B15
A12
B16
U10
A11
A8
K1
A9
U8
U5
L1
J1
HOLDOVER
RefAlign
JA19OE
JA77OE
JA19Mo
SECOR
RESET
PRIOR
RefSel
Name
LOCK
SEC
MS1
MS2
OE
Secondary Reference (Input). This input is a Secondary reference source for
synchronization. The module can synchronize to falling edge of the following
reference clocks: 8 kHz, 1.544 MHz, 2.048 MHz or the rising edge of 19.44 MHz.
This pin is selected when a logic 1 is applied to the RefSel input pin.
This pin is internally pulled to V
Primary Reference Rejection Range (Output). When used in Stratum 3
applications, a logic 1 at this output pin indicates that the Primary reference is off
the PLL centre frequency by more than ±12 ppm. This threshold is relative to the
accuracy of the 20 MHz master oscillator input OSCi.
Secondary Reference Rejection Range (Output). When used in Stratum 3
applications, a logic 1 at this output pin indicates that the Primary reference is off
the PLL centre frequency by more than ±12 ppm. This threshold is relative to the
accuracy of the 20 MHz master oscillator input OSCi.
Reference Source Select (Input). Logic 0 selects the PRI (Primary) reference
source as the input reference signal and logic 1 selects the SEC (Secondary) input.
The logic level at this input is sampled on the rising edge of F8o. This pin is
internally pulled to GND.
Reset (5 V tolerant Input). Logic 0 will forces the module into a reset state. This
pin must be held to logic 0 for a minimum of 1 µs to reset the module properly. The
module must be reset after power-up.
Lock Indicator (Output). Logic 1 at this output indicates that the clock synthesizer
outputs are locked to the selected input reference. Logic 0 indicates that the
selected input reference has exceeded (or is close to) the core PLL frequency
tracking range. This threshold is set at ±104 ppm and is relative to the accuracy of
the 20 MHz master oscillator input OSCi.
Holdover Indicator (Output). Logic 1 at this output indicates that the module is in
holdover.
Reference Align (Input). A high to low transition at this input initiates phase
realignment between the input reference and the generated output clocks.
This pin is internally pulled to GND.
Mode Select 1 (Input). The MS1 and MS2 inputs select the module’s mode of
operation (normal, holdover or free-run), see Table 1 for details. The logic level at
this input is sampled on the rising edge of the F8o frame pulse.
Mode Select 2 (Input). The MS2 and MS1 inputs select the module’s mode of
operation (normal, holdover or free-run), see Table 1 for details. The logic level at
this input is sampled on the rising edge of the F8o frame pulse.
Output Enable (Input). Logic 1 on this input enables C19o, F16o, C16o, C8o,
C6o, C4o, C2o, C1.5o, F8o and F0o signals. Logic 0 will force these output clocks
pins into a high impedance state.
JA19Mo Output Enable (Input). Logic 1 on this input will enable the JA19Mo
output clock and logic 0 will disable this it. (Note 1)
JA77P/N Output Enable (Input). Logic 1 on this input will enable the JA77P/N
output clock and logic 0 will disable this it. (Note 1)
JA 19.44 MHz Clock (Output). This output provides a low jitter 19.44 MHz clock.
Zarlink Semiconductor Inc.
ZL30461
3
DD1
.
Description
Data Sheet