ML22Q54 OKI [OKI electronic componets], ML22Q54 Datasheet - Page 8

• Manufacturer Part Number: ML22Q54
• Description: 2-Channel Mixing Oki ADPCM Algorithm-Based Speech Synthesis LSI
• Manufacturer: OKI [OKI electronic componets]

PIN DESCRIPTIONS-1
ML2252/54-XXX Common Pins
44-pin plastic QFP
OKI Semiconductor
16, 18, 19, 20
Pin
43
10
14
15
21
23
3
4
5
9
BUSY2 / ERR
NCR1/NDR
NCR2/ DL
Symbol
BUSY1
RESET
D5/DO
TEST
XT
D3
D2
D1
D0
D4
XT
Type
I/O
I/O
I/O
O
O
O
O
O
I
I
I
When using the built-in ROM for voice output, this pin outputs “L” level
while channel 2 side processes a command and while plays back
voice.
Works as ERR pin when using the EXT command for voice output. If an
abnormality occurred in the transfer of data, the pin will output “L” level
and the voice output may become noisy.
Outputs “L” level while the channel 1 side processes a command and
plays back voice.
The command input of channel 2 side is valid at “H” level when using
the built-in ROM for voice output.
Works as DL pin when using EXT command for the voice output. This
pin outputs the signal that captures voice data to inside. The data is
captured inside on the rising edge of DL .
“H” level at power on.
The command input of channel 1 side is valid at “H” level when using
the built-in ROM for voice output.
Works as NDR pin when using EXT command for the voice output. The
voice data input is valid at “H” level.
“H” level at power on.
At “L” level input, the device enters the initial state; the oscillation stops,
and AOUT output and DAQ output are GND level at this time.
Test pin for the device.
Input “L” level to this pin. This pin has a pull-down resistor built in.
Wired to a crystal or ceramic oscillator.
A feedback resistor of around 1 M is built in between this XT pin and
XT pin (pin 15).
When using an external clock, input the clock from this pin.
Wired to a ceramic or crystal oscillator.
When using an external clock, keep this pin open.
CPU interface data bus pins in the parallel input interface.
Channel status output pins at RD pin = “L” level.
In the serial input interface, keep these pins at “L” level.
CPU interface data bus pin in the parallel input interface.
When RD pin is at “L” level, this pin D4 usually outputs “L” level.
In the serial input interface, keep this pin at “L” level.
CPU interface data bus pin in the parallel input interface.
When RD pin is at “L” level, this D5/DO pin usually outputs “L” level.
Works as channel status output pin in the serial interface.
When CS and RD pins are “L” level, the status of each channel is output
serially from this D5/DO pin in synchronization with SCK clock.
“H” level at power on.
“H” level at power on.
Description
ML2252/54-XXX, ML22Q54
FEDL2250DIGEST-01
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