73K224L-28IH/F TERIDIAN [Teridian Semiconductor Corporation], 73K224L-28IH/F Datasheet - Page 16

• Manufacturer Part Number: 73K224L-28IH/F
• Description: Single-Chip Modem
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

SPECIAL REGISTER
BIT NO.
D7, D4, D0
D6
D5
D3
D2, D1
NOTE: This register is "mapped" and is accessed by setting CR2 bit D6 to a ONE and addressing CR3. This
Page: 16 of 31
101
SR
register provides functions to the 73K224L user that are not necessary in normal communications. Bits
D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be
returned to a ZERO.
D7
0
NAME
TXD SOURCE
TXBAUD CLK
RXUNDSCR
QUALITY
D2
SELECT
SIGNAL
0
0
1
1
LEVEL
DATA
TXBAUD
CLOCK
D1
0
1
0
1
D6
DESCRIPTION
NOT USED AT THIS TIME. Only write ZEROs to these bits.
TXBAUD clock is the transmit baud-synchronous clock that can be used to
synchronize the input of arbitrary quad/di-bit patterns. The rising edge of
TXBAUD signals the latching of a baud-worth of data internally. Synchronous
data to be entered via the TXDALT bit, CR3 bit D7, should have data transitions
that start 1/2 bit period delayed from the TXBAUD clock edges.
This bit outputs the data received before going to the descrambler.
This is useful for sending special unscrambled patterns that can be used for
signaling.
This bit selects the transmit data source; either the TXD pin if ZERO or the
TXDALT if this bit is a ONE. The TRANSMIT PATTERN bits D7 and D6 in CR1
override either of these sources.
THRESHOLD VALUE
The signal quality indicator is a logical ZERO when the signal received is
acceptable for low error rate reception. It is determined by the value of the Mean
Squared Error (MSE) calculated in the decision process when compared to a
given threshold. This threshold can be set to four levels of error rate. The SQI bit
will be low for good or average connections. As the error rate crosses the
threshold setting, the SQI bit will toggle at a 1.66 ms rate. Toggling will continue
until the error rate indicates that the data pump has lost convergence and a
retrain is required. At that point the SQI bit will be a ONE constantly. The SQI bit
and threshold selection are valid for QAM and DPSK only and indicates typical
error rate.
RXUN-
DSCR
DATA
D5
©
2005, 2008 TERIDIAN Semiconductor Corporation
10
10
10
10
-5
-6
-4
-3
D4
0
SOURCE
TXD
D3
UNITS
BER (default)
BER
BER
BER
V.22bis, V.22, V.21, Bell 212A, 103
SELECT1
QUALITY
SIGNAL
LEVEL
D2
DATA SHEET
Single-Chip Modem
SELECT0
QUALITY
SIGNAL
LEVEL
D1
73K224L
Rev 7.1
D0
0