AK4640_05 AKM [Asahi Kasei Microsystems], AK4640_05 Datasheet - Page 25

• Manufacturer Part Number: AK4640_05
• Description: 16-Bit ?? CODEC with MIC/HP/SPK-AMP
• Manufacturer: AKM [Asahi Kasei Microsystems]

ASAHI KASEI
(2) External mode (PMPLL bit = “0”)
When the PMPLL bit = “0”, the AK4640 works in external clock mode. The MCKO pin outputs a buffered clock of
MCKI input.
For example, when MCKI = 256fs, the sampling frequency is changeable from 8kHz to 48kHz (Table 7). The MCKO bit
enables MCKO output. The frequency of MCKO is selectable via register the PS1-0 bits as defined in Table 8. If PS1-0
bits are changed before LRCK is input, MCKO is not output. PS1-0 bits should be changed after LRCK
is input in slave mode. ). If the master clock frequency is changed when the ADC or the DAC operates (PMADC bit
= “1” or PMDAC bit = “1”), the click noise may occur. The mute sequence examples (Figure 53 and Figure 54,
respectively) are available to reduce the click noise of headphone and speaker amps.
LRCK and BICK are output from the AK4640 in master mode. The clock to the MCKI pin must not stop during normal
operation (PMPLL bit = “1”). If this clock is not provided, the AK4640 may draw excess current due to its use of internal
dynamically refreshed logic. If the external clocks are not present, place the AK4640 in power-down mode (PMADC bit
= PMDAC bit = “0”).
MCKI, BICK and LRCK clocks are required in slave mode. The master clock (MCKI) should be synchronized with
sampling clock (LRCK). The phase between these clocks does not matter. LRCK and BICK should always be present
whenever the AK4640 is in normal operation (PMADC bit = “1” or PMDAC bit = “1”). If these clocks are not provided,
the AK4640 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK4640 in power-down mode (PMADC bit = PMDAC bit = “0”).
MS0273-E-02
MCKO pin
LRCK pin
MCKI pin
BICK pin
Mode
MCKO pin
MCKI pin
LRCK pin
BICK pin
0
1
2
3
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
Input
Input
Power up
Frequency set by PLL1-0
bits (Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Output
BF bit = “0” : 64fs Output
BF bit = “1” : 32fs Output
Output
FS1
0
0
1
1
Table 5. Clock Operation at Master Mode (PLL Mode)
Table 6. Clock Operation at Slave Mode (PLL Mode)
Table 7. Sampling Frequency Select (EXT Mode)
FS0
0
1
0
1
Power down
Fixed to “L” or “H” externally
Fixed to “L” or “H” externally
Master Mode (M/S pin = “H”)
Slave Mode (M/S pin = “L”)
Sampling Frequency (fs)
- 25 -
Refer to Table 1
Power down
Refer to Table 1
8kHz ∼ 48kHz
8kHz ∼ 24kHz
8kHz ∼ 12kHz
8kHz ∼ 48kHz
“L”
“L”
“L”
“L”
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
PLL Unlock
Frequency set by PLL1-0 bits
(Refer to Table 2)
MCKO bit = “0” : “L”
MCKO bit = “1” : Unsettling
1024fs
MCKI
256fs
512fs
256fs
“L”
“L”
Input
Input
Default
[AK4640]
2005/04