AK4640_05 AKM [Asahi Kasei Microsystems], AK4640_05 Datasheet
AK4640_05
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AK4640_05 Summary of contents
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ASAHI KASEI The AK4640 targeted at PDA and other low-power, small size applications. It features a 16bit stereo CODEC with a built-in Microphone-Amplifier, Headphone-Amplifier and Speaker-Amplifier. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit. The AK4640 ...
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ASAHI KASEI 11. Audio Interface Format : MSB First, 2’s compliment • ADC : 16bit MSB justified • DAC : 16bit MSB justified, 16bit LSB justified 12 −10 ∼ 70°C 13. Power ...
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ASAHI KASEI Ordering Guide −10 ∼ +70°C AK4640VG −10 ∼ +70°C AK4640VN AKD4640 Evaluation board for AK4640 Pin Layout (AK4640VG HPR HVSS 8 HPL MUTET HVSS 7 MIN NC ...
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ASAHI KASEI Pin Layout (AK4640VN) MIN 40 MOUT2 MOUT− 44 MOUT+ 45 AUXIN− 46 AUXIN+ 47 BEEPM 48 BEEPR 49 BEEPL 50 AIN MS0273-E-02 AK4640 Top View - 4 - [AK4640] NC ...
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ASAHI KASEI Comparison with AK4534, AK4538 1. Function Function SPK-Amp Output Power at DAC path DAC Digital Filter Stopband Attenuation AUX Input MOUT Gain Select Path from IPGA to Analog Output HP-Amp Mono mode Stereo Line Out MIC Detect HP-Amp ...
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ASAHI KASEI No. Pin Name I/O No Connect internal bonding. This pin should be left floating. B1 EXT I External Microphone Input Pin C1 MPE O MIC Power Supply Pin for External Microphone C2 MPI O ...
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ASAHI KASEI No. Pin Name I/O No Connect internal bonding. This pin should be left floating. J8 DVSS - Digital Ground Pin G8 XTO O X’tal Output Pin XTI I X’tal Input Pin H9 MCKI I ...
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ASAHI KASEI No. Pin Name I/O 1 MICOUT O Microphone Analog Output Pin No Connect internal bonding. This pin should be left floating. 3 EXT I External Microphone Input Pin (Mono Input) 4 MPE O MIC ...
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ASAHI KASEI No. Pin Name I/O No Connect internal bonding. This pin should be left floating. 28 DVDD - Digital Power Supply Pin 29 DVSS - Digital Ground Pin 30 XTO O X’tal Output Pin XTI ...
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ASAHI KASEI (AVSS, DVSS, PVSS, HVSS=0V; Note 1) Parameter Power Supplies: Analog Digital PLL Headphone-Amp / Speaker-Amp |AVSS – PVSS| |AVSS – DVSS| |AVSS – HVSS| Input Current, Any Pin Except Supplies Analog Input Voltage Digital Input Voltage Ambient Temperature ...
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ASAHI KASEI (Ta=25°C; AVDD, DVDD, PVDD, HVDD=3.3V; AVSS=DVSS=PVSS=HVSS=0V; fs=44.1kHz, BICK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz ∼ 20kHz; unless otherwise specified) Parameter MIC Amplifier: Input Resistance (MGAIN bit = “0”) Gain (MGAIN bit = “1”) MIC Power Supply: Output Voltage ...
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ASAHI KASEI Parameter Headphone-Amp Characteristics: R Output Voltage (Note 8) S/(N+D) (−3dBFS) S/N (A-weighted) Interchannel Isolation Interchannel Gain Mismatch Load Resistance (C1 in Figure 2) Load Capacitance (C2 in Figure 2) =8Ω, BTL, DAC → MOUT2 pin → MIN pin ...
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ASAHI KASEI Parameter Mono Input: MIN pin Maximum Input Voltage (Note 11) Input Resistance (Note 12) =10kΩ, DAC → MIX → MOUT2 pin Mono Output Output Voltage (Note 13) Load Resistance Load Capacitance (Note 14) AUX Input: AUXIN+, ...
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ASAHI KASEI (Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V; fs=44.1kHz; DEM=OFF) Parameter ADC Digital Filter (Decimation LPF): ±0.1dB Passband (Note 20) −1.0dB −3.0dB Stopband Passband Ripple Stopband Attenuation Group Delay (Note 21) Group Delay Distortion ADC Digital Filter ...
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ASAHI KASEI (Ta=−10 ∼ 70°C; AVDD, DVDD, PVDD, HVDD=2.4 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage Input Voltage at AC Coupling High-Level Output Voltage Low-Level Output Voltage (Except SDA pin: Iout=200µA) (SDA pin: Iout=3mA) Input Leakage Current Note ...
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ASAHI KASEI Parameter Control Interface Timing (4-wire Serial mode): CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN “H” Time CSN “↓” to CCLK “↑” CCLK “↑” to CSN “↑” CDTO Delay CSN ...
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ASAHI KASEI Timing Diagram MCLK tCLKH LRCK BICK tBCKH MCKO dMCK 1000pF MCKI Input MS0273-E-02 1/fCLK tCLKL 1/fs tBCK tBCKL fMCK dMCK Figure 3. Clock Timing Measurement Point 100kΩ AGND AGND Figure 4. MCKI AC Coupling Timing - 17 - ...
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ASAHI KASEI LRCK tBLR BICK tLRS SDTO SDTI Figure 5. Audio Interface Timing (Slave mode) LRCK tMBLR BICK SDTO SDTI Figure 6. Audio Interface Timing (Master mode) MS0273-E-02 tLRB tBSD tSDS tSDH dBCK tBSD tSDS tSDH - 18 - [AK4640] ...
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ASAHI KASEI CSN CCLK CDTI CDTO Figure 7. WRITE/READ Command Input Timing CSN CCLK CDTI D2 CDTO MS0273-E-02 tCSS tCCKL tCCKH tCDS tCDH C1 C0 Hi-Z tCSH D1 D0 Hi-Z Figure 8. WRITE Data Input Timing - 19 - [AK4640] ...
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ASAHI KASEI CSN CCLK CDTI A1 Hi-Z CDTO CSN CCLK CDTI CDTO D2 MS0273-E-02 A0 tDCD D7 Figure 9. READ Data Output Timing 1 tCSW tCSH D1 D0 Figure 10. READ Data Output Timing [AK4640] VIH ...
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ASAHI KASEI SDA tBUF tLOW tR SCL tHD:STA Stop Start PMADC bit SDTO PDN MS0273-E-02 tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 11 Bus Mode Timing tPDV tPD Figure 12. Power Down & Reset Timing - 21 ...
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ASAHI KASEI Master Clock Source The AK4640 requires a master clock (MCKI). This master clock is input to the AK4640 by connecting a X’tal oscillator to XTI and XTO pins or by inputting an external CMOS-level clock to the XTI ...
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ASAHI KASEI (2) External Clock Direct Input XTI External Clock XTO Figure 14. External Clock mode (Input: CMOS Level) Note: This clock level must not exceed DVDD level. (3) AC Coupling Input C XTI External Clock XTO Figure 15. External ...
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ASAHI KASEI System Clock (1) PLL Mode (PMPLL bit = “1”) A fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL1-0 and FS2-0 bits (see Table 2 and Table 3). The frequency of ...
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ASAHI KASEI Power up Frequency set by PLL1-0 MCKI pin bits (Refer to Table 2) MCKO bit = “0” : “L” MCKO pin MCKO bit = “1” : Output BF bit = “0” : 64fs Output BICK pin BF bit ...
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ASAHI KASEI Mode Table 8. MCKO Frequency (EXT Mode, MCKO bit = “1”) MCKO pin BICK pin LRCK pin Table 9. Clock Operation at Master Mode (EXT Mode) Power up MCKO bit = “0” : “L” ...
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ASAHI KASEI System Reset Upon power-up, reset the AK4640 by bringing the PDN pin = “L”. This ensures that all internal registers are reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit ...
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ASAHI KASEI LRCK BICK(32fs SDTO( SDTI( BICK(64fs SDTO( SDTI(i) 15:MSB, 0:LSB LRCK BICK(32fs) SDTO( ...
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ASAHI KASEI MIC Gain Amplifier AK4640 has a Gain Amplifier for Microphone input. This gain is 0dB or +20dB, selected by the MGAIN bit (Table 14). The typical input impedance is 30kΩ. MIC Power The MPI and MPE pins supply ...
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ASAHI KASEI Manual Mode The AK4640 becomes a manual mode at ALC1 bit = “0”. This mode is used in the case shown below. 1. After exiting reset state, set up the registers for the ALC1 operation (ZTM1-0, LMTH and ...
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ASAHI KASEI (3) Example of ALC1 Operation Table 15 shows the examples of the ALC1 setting. In case of this examples, ALC1 operation starts from 0dB. Register Name Comment LMTH Limiter detection Level LTM1-0 Limiter operation period at ZELM = ...
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ASAHI KASEI De-emphasis Filter The AK4640 includes the digital de-emphasis filter (tc = 50/15µs) by IIR filter. Setting the DEM1-0 bits enables the de-emphasis filter (Table 16). DEM1 Bass Boost Function The BST1-0 bits control the ...
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ASAHI KASEI Digital Attenuator The AK4640 has a channel-independent digital attenuator (256 levels, 0.5dB step, Mute). The ATTL/R7-0 bits control the attenuation level of each channel. When the DATTC bit = “1”, the ATTL7-0 bits control both Lch and Rch ...
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ASAHI KASEI AUX Input AUXIN+ AUXIN− AUX input is differential input. The AK4640 has a volume for AUX Input. GN3-0 bits control this Volume as shown in Table 19. The switching noise occurs when GN3-0 bits are changed. MS0273-E-02 “GN3-0” ...
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ASAHI KASEI BEEP Input When the PMBPS bit is set to “1”, the stereo beep input is powered up. And when the BPSHP bit is set to “1”, the input signals from the BEEPL and BEEPR pins are mixed to ...
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ASAHI KASEI Headphone Output Power supply voltage for the Headphone-amp is supplied from the HVDD pin and centered on the HVDD/2 voltage. The Headphone output load resistance is min.20Ω. When the PMHPL and PMHPR bits are “0”, the common voltage ...
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ASAHI KASEI The cut-off frequency of Headphone-amp output depends on the external resistor and capacitor used. Table 21 shows the cut off frequency and the output power for various resistor/capacitor combinations. The headphone impedance R Output powers are shown at ...
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ASAHI KASEI Speaker Output The output signal from analog volume is converted into a mono signal [(L+R)/2] and this signal is input to the Speaker-amp via the ALC2 circuit. This Speaker-amp is a mono output controlled by BTL and can ...
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ASAHI KASEI 2) Using BEEPL and BEEPR pins AK4640 MOUT2 0.068u 20k 20k Figure 29. Connection example for 400mW output using BEEPL and BEEPR pins Note) 1. MOUT2 output is recommended coupled to avoid amplified DC offset ...
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ASAHI KASEI Mono Output (MOUT+/MOUT− pins) MICOUT pin AIN pin MIC In +20dB/0dB IPGA Lch ATT+DAC When DAMO bit is “1”, mono mixer mixes Lch and Rch signal from DAC. This mixed signal is output to mono line output that ...
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ASAHI KASEI ALC2 Operation Input resistance of the ALC2 (MIN pin) is 24kΩ (typ) and centered around VCOM voltage. (see Figure 31. 0dBV=1Vrms =2.828Vpp) The limiter detection level is proportional to HVDD. The ALC2 circuit limits the output level when ...
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ASAHI KASEI Serial Control Interface (1) 4-wire Serial Control Mode (I2C pin = “L”) Internal registers may be written by using the 4-wire µP interface pins (CSN, CCLK, CDTI and CDTO). The data on this interface consists of a 2-bit ...
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ASAHI KASEI 2 (2) I C-bus Control Mode (I2C pin = “H”) The AK4640 supports the standard-mode I system (max: 400kHz). (2)-1. WRITE Operations Figure 33 shows the data transfer sequence for the I HIGH to LOW transition on the ...
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ASAHI KASEI (2)-2. READ Operations Set the R/W bit = “1” for the READ operation of the AK4640. After transmission of data, the master can read the next address’s data by generating an acknowledge instead of terminating the write cycle ...
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ASAHI KASEI SDA SCL S start condition DATA OUTPUT BY TRANSMITTER DATA OUTPUT BY RECEIVER SCL FROM MASTER S START CONDITION SDA SCL MS0273-E-02 Figure 39. START and STOP Conditions Figure 40. Acknowledge on the I C-Bus ...
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ASAHI KASEI Register Map Addr Register Name D7 00H Power Management 1 PMVCM 01H Power Management 2 MCKPD 02H Signal Select 1 MOGN 03H Signal Select 2 DAHS 04H Mode Control 1 PLL1 05H Mode Control 2 FS2 06H DAC ...
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ASAHI KASEI Register Definitions Addr Register Name D7 00H Power Management 1 PMVCM R/W R/W Default 0 PMADC: ADC Block Power Control 0: Power down (Default) 1: Power up When the PMADC bit changes from “0” to “1”, the initialization ...
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ASAHI KASEI Addr Register Name D7 01H Power Management 2 MCKPD R/W R/W Default 1 PMDAC: DAC Block Power Control 0: Power down (Default) 1: Power up PMHPR: Rch of Headphone-Amp Common Voltage Power Control 0: Power down (Default) 1: ...
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ASAHI KASEI Addr Register Name 02H Signal Select 1 MOGN R/W Default MOUT2: MOUT2 Output Enable (Mixing = (L+R)/2) 0: OFF (Default When the MOUT2 bit = “0”, the MOUT2 pin outputs VCOM voltage. The MOUT2 pin outputs ...
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ASAHI KASEI MIC In 0dB/+20dB ATT+DAC AUXIN+ AUXIN- Volume BEEPM BEEPL BEEPR Addr Register Name 03H Signal Select 2 DAHS R/W Default HPR: Rch of Headphone-Amp Power Control 0: Normal Operation 1: OFF(Default) HPL: Lch of Headphone-Amp Power Control 0: ...
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ASAHI KASEI DAHS: DAC to Headphone-amp and MOUT2 Enable 0: OFF (Default DAC signal is mixed to Headphone-amp and MOUT2 at the DAHS bit = “1”. MIC IN 0dB/+20dB ATT+DAC AUXIN+ AUXIN- Volume BEEPM IN BEEPL IN BEEPR ...
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ASAHI KASEI Addr Register Name 04H Mode Control 1 R/W Default DIF1-0: Audio Interface Format Select (Table 13) 2 Default: “10” (ADC DAC: I BF: BICK frequency Select at Master Mode 0: 64fs (Default) 1: 32fs This bit ...
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ASAHI KASEI Addr Register Name 05H Mode Control 2 R/W Default SPPS: Speaker-amp Power-Save-Mode 0: Power Save Mode (Default) 1: Normal Operation When the SPPS bit = “1”, the Speaker-amp is in power-save-mode and the SPP pin becomes Hi-Z and ...
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ASAHI KASEI Addr Register Name 06H DAC Control R/W Default DEM1-0: De-emphases response (Table 16) Default is “01” (OFF). BST1-0: Select Low Frequency Boost Function (Table 17) Default is “00” (OFF). DATTC: DAC Digital Attenuator Control Mode Select 0: Independent ...
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ASAHI KASEI Addr Register Name D7 07H MIC/HP Control R/W RD Default st MGAIN: 1 Mic-amp Gain control 0: 0dB 1: +20dB (Default) MSEL: Microphone select 0: Internal MIC (Default) 1: External MIC MICAD: Switch Control from Mic In to ...
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ASAHI KASEI Addr Register Name 08H Timer Select R/W Default LTM1-0: ALC1 limiter operation period at zero crossing disable (see Table 25) The IPGA value is changed immediately. When the IPGA value is changed continuously, the change is done by ...
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ASAHI KASEI Addr Register Name 09H ALC Mode Control 1 R/W Default LMTH: ALC1 Limiter Detection Level / Recovery Waiting Counter Reset Level (see Table 28) The ALC1 limiter detection level and the ALC1 recovery counter reset level may be ...
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ASAHI KASEI ALC1: ALC1 Enable 0: ALC1 Disable (Default) 1: ALC1 Enable ALC2: ALC2 Enable 0: ALC2 Disable 1: ALC2 Enable (Default) Addr Register Name 0AH ALC Mode Control 2 R/W Default REF6-0: Reference value at ALC1 Recovery Operation (see ...
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ASAHI KASEI Addr Register Name 0BH Input PGA Control R/W Default IPGA6-0: Input Analog PGA (see Table 32) Default: “10H” (0dB) When IPGA gain is changed, IPGA6-0 bits should be written while PMMIC bit is “1” and ALC1 bit is ...
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ASAHI KASEI Addr Register Name 0EH Volume Control ATTM R/W Default GN3-0: Volume Control of AUX In (see Table 19) ATTS2-0: Attenuator select of signal from MIC IN to Stereo Mixer (see Table 33) ATTS2-0 ATTM: Attenuator control for signal ...
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ASAHI KASEI Figure 44 shows the system connection diagram for the AK4640VG. An evaluation board [AKD4640] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 1µ 2.2k 2.2k 1µ 0.1µ 2.2µ Analog Supply 10µ 0.1µ 2.4 ...
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ASAHI KASEI Figure 45 shows the system connection diagram for the AK4640VN. An evaluation board [AKD4640] is available which demonstrates the optimum layout, power supply arrangements and measurement results. 1µ 1 MICOUT 2 NC 1µ 3 EXT 2.2k 4 MPE ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling The AK4640 requires careful attention to power supply and grounding arrangements. AVDD, DVDD, PVDD and HVDD are usually supplied from the system’s analog supply. If AVDD, DVDD, PVDD and HVDD are supplied ...
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ASAHI KASEI Power up Upon power-up, bring the PDN pin = “L”. Initialize the internal registers to default values after the PDN pin = “H”. When the power supplies are partially powered OFF, the AK4640 must be reset by bringing ...
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ASAHI KASEI Clock Set up When ADC, DAC, ALC1 and ALC2 are used, the clocks (MCKI, BICK and LRCK) must be supplied. 1. When X'tal is used in PLL mode. (Slave mode) MCKPD bit (Addr:01H, D7) (1) PMXTL bit (Addr:01H, ...
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ASAHI KASEI 2. When X'tal is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) PMXTL bit (Addr:01H, D6) 20ms(typ) (2) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) (3) PS1-0 bits 00 (Addr:04H, D5-4) MCKO pin BICK, ...
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ASAHI KASEI 3. When an external clock is used in PLL mode. (Slave mode) (1) MCKPD bit (Addr:01H, D7) (2) External MCLK (3) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) (4) MCKO pin BICK, LRCK (Slave Mode) PS1-0 bits ...
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ASAHI KASEI 4. When an external clock is used in PLL mode. (Master mode) MCKPD bit (Addr:01H, D7) (1) (2) External MCLK (3) PMPLL bit (Addr:01H, D5) MCKO bit (Addr:04H, D3) PS1-0 bits 00 (Addr:04H, D5-4) MCKO pin BICK, LRCK ...
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ASAHI KASEI MIC Input Recording FS2-0 bits 000 (Addr:05H, D7-5) (1) MIC Control 00001 (Addr:07H, D2-0) (2) ALC1 Control 1 XXH (Addr:08H) (3) ALC1 Control 2 XXH (Addr:0AH) (4) ALC1 Control 3 XXH (Addr:09H) (5) ALC1 State ALC1 Disable PMADC ...
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ASAHI KASEI Headphone-amp Output FS2-0 bits 000 (Addr:05H, D7-5) (1) BST1-0 bits 00 (Addr:06H, D3-2) (2) ATTL7-0 bits 0000000 (Addr:0CH 0DH, D7-0) (3) PMDAC bit (Addr:01H, D0) HPL/R bit (Addr:03H, D1-0) PMHPL/R bits (Addr:01H, D2-1) HPL/R pins Figure 53. Headphone-Amp ...
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ASAHI KASEI Speaker-amp Output FS2-0 bits 000 (Addr:05H, D7-5) (1) ALC2 bit 0 (Addr:09H, D6 (2) ATTL7-0 bits 0000000 (Addr:0CH 0DH, D7-0) (3) PMDAC bit (Addr:01H, D0) (4) PMSPK bit (Addr:01H, D3) SPPS bit (Addr:05H, D0) SPP pin Hi-Z SPN ...
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ASAHI KASEI Stop of Clock MCKI can be stopped when PMMIC=PMADC=PMDAC=PMSPK= “0”. 1. When X’tal is used in PLL mode (1) MCKO bit (Addr:03H, D4) PMXTL bit (Addr:01H, D6) (2) PMPLL bit (Addr:01H, D5) MCKPD bit (Addr:01H, D7) <Example> (1) ...
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ASAHI KASEI 3. External clock mode r xtern <Example> (1) Pull down the XTI ...
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ASAHI KASEI 57pin BGA (Unit: mm) 5.0 ± 0.1 Material & Lead finish Package molding compound: Interposer material: Solder ball material: MS0273-E-02 PACKAGE (AK4640VG φ 0.3 ± 0.05 φ 0. 0.5 S 0.08 S Epoxy ...
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ASAHI KASEI 52pin QFN (Unit: mm) 7.2 ± 0.20 7.0 ± 0. 0.05 Note) The part of black at four corners on reverse side must not be soldered and must be open. Material & Lead finish ...
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ASAHI KASEI MS0273-E-02 MARKING (AK4640VG) 4640 XXXX XXXX: Date code (4 digit) Pin #1 indication - 76 - [AK4640] 2005/04 ...
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ASAHI KASEI XXXXXXX : Date (YY/MM/DD) Revision Reason 04/03/16 00 First Edition 04/11/26 01 Explanation addition: 05/04/27 02 Explanation change: Error correct MS0273-E-02 MARKING (AK4640VN) AKM AK4640VN XXXXXXX 1 Date code identifier (7 digits) Revision History Page Contents 27 Audio ...
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ASAHI KASEI • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. • AKM assumes ...