AK4632VN AKM [Asahi Kasei Microsystems], AK4632VN Datasheet - Page 58
AK4632VN
Manufacturer Part Number
AK4632VN
Description
16-Bit ?? Mono CODEC with ALC & MIC/SPK/Video-AMP
Manufacturer
AKM [Asahi Kasei Microsystems]
Datasheet
1.AK4632VN.pdf
(70 pages)
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ASAHI KASEI
MS0396-E-00
2. When the external clocks (FCK or BICK pin) are used in PLL Slave Mode.
<Example>
Power Supply
Internal Clock
(Addr:00H, D6)
(Addr:01H, D2)
(Addr:01H, D0)
PMVCM bit
MCKPD bit
PMPLL bit
(1) After Power Up: PDN pin “L” → “H”
(2) DIF1-0, FS3-0, PLL3-0, MSBS and BCKP bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” → “1”
(4) Pull down of the MCKI pin: MCKPD bit = “1”
(5) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (FCK or BICK pin) is supplied.
(6) Normal operation stats after the PLL is locked.
BICK pin
FCK pin
PDN pin
PLL lock time is 160ms(max) when FCK is a PLL reference clock. And PLL lock time is 2ms(max) when BICK
is a PLL reference clock.
“L” time (1) of 150ns or more is needed to reset the AK4632.
VCOM should first be powered up before the other block operates.
(1)
(2)
(3)
(4)
"H"
Figure 47. Clock Set Up Sequence (2)
Input
(5)
- 58 -
(6)
4fs of
(1) Power Supply & PDN pin = “L”
Example:
Audio I/F Format : DSP Mode, BCKP = MSBS = “0”
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 8kHz
(2) Addr:04H, Data:30H
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:05H
Addr:05H, Data:00H
BICK and FCK input
[AK4632]
“H”
2005/06
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