AM29SL160C AMD [Advanced Micro Devices], AM29SL160C Datasheet - Page 11

• Manufacturer Part Number: AM29SL160C
• Description: 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register itself
does not occupy any addressable memory location.
The register is composed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend:
L = Logic Low = V
D
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See
3. If WP#/ACC = V
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
November 1, 2004
Read
Write
(Program/Erase)
Standby
Output Disable
Reset
Sector Protect
(Note 2)
Sector Unprotect
(Note 2)
Temporary Sector
Unprotect
OUT
Block Protection and Unprotection” on page
protected or unprotected as previously set by the system. If WP#/ACC = V
sectors, are unprotected.
= Data Out
Operation
IL
, H = Logic High = V
IL
, the two outermost boot sectors are protected. If WP#/ACC = V
V
0.2 V
CE#
CC
X
X
L
L
L
L
L
±
OE# WE# RESET# WP#/ACC
H
X
H
X
H
H
X
L
Table 1. Am29SL160C Device Bus Operations
H
X
H
X
X
L
L
L
IH
, V
ID
V
0.2 V
= 10 ± 1.0 V, V
V
V
V
CC
17.
H
H
H
L
ID
ID
ID
±
IH
), A19:A-1 in byte mode (BYTE# = V
Am29SL160C
(Note 3)
(Note 3)
(Note 3)
X
X
X
X
X
HH
= 10 ± 0.5 V, X = Don’t Care, A
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
Sector Address,
Sector Address,
A6 = H, A1 = H,
A6 = L, A1 = H,
Addresses
(Note 1)
A0 = L
A0 = L
A
A
A
X
X
X
IN
IN
IN
Table 1
HH
, all sectors, including the two outermost boot
IH
lists the device bus operations, the
, the two outermost boot sectors are
High-Z
High-Z
High-Z
DQ0–
D
DQ7
D
D
D
D
OUT
IN
IN
IN
IN
IH
IL
. The BYTE# pin determines
).
BYTE#
High-Z
High-Z
High-Z
IN
= V
D
D
D
OUT
X
X
= Address In, D
IN
IN
IH
IL
DQ8–DQ14 = High-Z,
DQ8–DQ15
. CE# is the power
DQ15 = A-1
BYTE#
“Sector/Sector
High-Z
High-Z
High-Z
High-Z
= V
X
X
IN
IL
= Data In,
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