M37212 Mitsubishi, M37212 Datasheet - Page 34

• Manufacturer Part Number: M37212
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
• Manufacturer: Mitsubishi

8.6.3 I
The I
control, SCL mode and SCL frequency.
(1) Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency.
(2) Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
(3) Bit 6: ACK bit (ACK BIT)
This bit sets the SDA status when an ACK clock is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
Fig. 8.6.4 I
34
ACK clock: Clock for acknowledgement
2
C clock control register (address 00DB
2
C Clock Control Register
2
C Address Register
I
2
C C l o c k C o n t r o l R e g i s t e r
b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
N o t e : A t 4 0 0 k H z i n t h e h i g h - s p e e d c l o c k m o d e , t h e d u t y i s a s b e l o w .
t o
B
0
4
5
6
7
I
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
2
C c l o c k c o n t r o l r e g i s t e r ( S 2 ) [ A d d r e s s 0 0 D B
16
S C L f r e q u e n c y c o n t r o l b i t s
( C C R 0 t o C C R 4 )
S C L m o d e
( F A S T M O D E )
A C K b i t
( A C K B I T )
A C K c l o c k b i t
( A C K )
s p e c i f i c a t i o n b i t
) is used to set ACK
“ 0 ” p e r i o d : “ 1 ” p e r i o d = 3 : 2
I n t h e o t h e r c a s e s , t h e d u t y i s a s b e l o w .
“ 0 ” p e r i o d : “ 1 ” p e r i o d = 1 : 1
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
N a m e
S e t u p v a l u e o f
C C R 4 – C C R 0
0 : S t a n d a r d c l o c k m o d e
1 : H i g h - s p e e d c l o c k m o d e
0 : A C K i s r e t u r n e d .
1 : A C K i s n o t r e t u r n e d .
0 : N o A C K c l o c k
1 : A C K c l o c k
0 0 t o 0 2
(4) Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit generated
by the data receiving device.
Note: Do not write data into the I
1 D
1 E
0 3
0 4
0 5
0 6
1 F
If data is written during transmission, the I
that data cannot be transmitted normally.
5 0 0 / C C R v a l u e 1 0 0 0 / C C R v a l u e
S t a n d a r d c l o c k
S e t u p d i s a b l e d S e t u p d i s a b l e d
S e t u p d i s a b l e d
S e t u p d i s a b l e d
1 6
( a t
]
F u n c t i o n s
m o d e
8 3 . 3
1 7 . 2
1 6 . 6
1 6 . 1
1 0 0
= 4 M H z , u n i t : k H z )
with ON-SCREEN DISPLAY CONTROLLER
4 0 0 ( S e e n o t e )
H i g h s p e e d
c l o c k m o d e
MITSUBISHI MICROCOMPUTERS
3 4 . 5
3 3 . 3
3 2 . 3
3 3 3
2 5 0
1 6 6
2
C clock control register during transmission.
M37212EFSP/FP
A f t e r r e s e t R W
0
0
0
0
2
C clock generator is reset, so
R W
R W
R W
R W
Rev. 1.0