M37212 Mitsubishi, M37212 Datasheet - Page 33

• Manufacturer Part Number: M37212
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
• Manufacturer: Mitsubishi

8.6.2 I
The I
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
(1) Bit 0: read/write bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
(2) Bits 1 to 7: slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
Fig. 8.6.3 I
Rev. 1.0
2
C address register (address 00D8
2
C Address Register
2
C Address Register
I
2
b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0
C A d d r e s s R e g i s t e r
16
) consists of a 7-bit slave
I
t o
B
0
1
7
2
M37212M4/M8–XXXSP, M37212M6–XXXSP/FP
C a d d r e s s r e g i s t e r ( S 0 D ) [ A d d r e s s 0 0 D 8
R e a d / w r i t e b i t
( R B W )
S l a v e a d d r e s s
( S A D 0 t o S A D 6 )
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER for VOLTAGE SYNTHESIZER
N a m e
2
C
< O n l y i n 1 0 - b i t a d d r e s s i n g ( i n s l a v e ) m o d e >
T h e l a s t s i g n i f i c a n t b i t o f a d d r e s s d a t a i s
c o m p a r e d .
0 : W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r
1 : W a i t t h e f i r s t b y t e o f s l a v e a d d r e s s a f t e r
< I n b o t h m o d e s >
T h e a d d r e s s d a t a i s c o m p a r e d .
S T A R T c o n d i t i o n
R E S T A R T c o n d i t i o n
F u n c t i o n s
1 6
with ON-SCREEN DISPLAY CONTROLLER
]
MITSUBISHI MICROCOMPUTERS
( r e a d s t a t e )
( w r i t e s t a t e )
M37212EFSP/FP
A f t e r r e s e t R W
0
0
R —
R W
33