GS841E18AGT-150I GSI Technology, GS841E18AGT-150I Datasheet

GS841E18AGT-150I

Manufacturer Part Number

GS841E18AGT-150I

Description

Manufacturer

GSI Technology

Datasheet

1.GS841E18AGT-150I.pdf (21 pages)

Specifications of GS841E18AGT-150I

Pack_quantity

Comm_code

85423245

Lead_time

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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• 3.3 V +10%/–5% core power supply, 2.5 V or 3.3 V I/O

• Dual Cycle Deselect (DCD)

• Intergrated data comparator for Tag RAM application

• FT mode pin for flow through or pipeline operation

• LBO pin for Linear or Interleave (Pentium

• Synchronous address, data I/O, and control inputs

• Synchronous Data Enable (DE)

• Asynchronous Output Enable (OE)

• Asynchronous Match Output Enable (MOE)

• Byte Write (BWE) and Global Write (GW) operation

• Three chip enable signals for easy depth expansion

• Internal self-timed write cycle

• JTAG Test mode conforms to IEEE standard 1149.1

• JEDEC-standard 100-lead TQFP package and 119-BGA

• RoHS-compliant 100-lead TQFP and 119-bump BGA

Functional Description

The GS841E18A is a 256K x 18 high performance synchronous DCD

SRAM with integrated Tag RAM comparator. A 2-bit burst counter is

included to provide burst interface with Pentium

performance CPUs. It is designed to be used as a Cache Tag SRAM,

as well as data SRAM. Addresses, data IOs, match output, chip

enables (CE1, CE2, CE3), address control inputs (ADSP, ADSC,

ADV), and write control inputs (BW1, BW2, BWE, GW, DE) are

synchronous and are controlled by a positive-edge-triggered clock

(CLK).

Output Enable (OE), Match Output Enable, and power down control

(ZZ) are asynchronous. Burst can be initiated with either ADSP or

ADSC inputs. Subsequent burst addresses are generated internally and

are controlled by ADV. The burst sequence is either interleave order

(Pentium

Rev: 1.03a 10/2006

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. * Pentium is a trademark of Intel

supply

mode

packages available

or x86) or linear order, and is controlled by LBO.

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

cycle

and other high

and X86) Burst

256K x 18 Sync

335 mA

210 mA

5.5 ns

3.2 ns

9.1 ns

–180

Parameter Synopsis

8 ns

Cache Tag

1/21

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

-166

Output registers and the Match output register are provided and

controlled by the FT mode pin (Pin 14). Through use of the FT mode

pin, I/O registers can be programmed to perform pipeline or flow

through operation. Flow Through mode reduces latency.

Byte write operation is performed by using Byte Write Enable (BWE)

input combined with two individual byte write signals BW1-2. In

addition, Global Write (GW) is available for writing all bytes at one

time.

Compare cycles begin as a read cycle with output disabled so that

compare data can be loaded into the data input register. The

comparator compares the read data with the registered input data and a

match signal is generated. The match output can be either in Pipeline

or Flow Through modes controlled by the FT signal.

Low power (Standby mode) is attained through the assertion of the ZZ

signal, or by stopping the clock (CLK). Memory data is retained

during Standby mode.

JTAG boundary scan interface is provided using IEEE standard

1149.1 protocol. Four pins—Test Data In (TDI), Test Data Out

(TDO), Test Clock (TCK) and Test Mode Select (TMS)—are used to

perform JTAG function.

The GS841E18A operates on a 3.3 V power supply and all inputs/

outputs are 3.3 V- or 2.5 V-LVTTL-compatible. Separate output

Dual Cycle Deselect (DCD)

The GS841E18A is a DCD pipelines synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. DCD SRAMs hold the deselect command for one full

cycle and then begin turning off their outputs just after the second

rising edge of the clock.

DDQ

275 mA

190 mA

6.6 ns

3.8 ns

10 ns

) pins are used to allow both 3.3 V or 2.5 V IO interface.

-150

GS841E18AT/B-180/166/150/130/100

250 mA

140 mA

7.5 ns

4.0 ns

15 ns

11 ns

-133

190 mA

140 mA

4.5 ns

10 ns

12 ns

15 ns

-100

3.3 V and 2.5 V I/O

180 MHz–100 MHz

3.3 V V

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