GS4576C09L-33I GSI Technology, GS4576C09L-33I Datasheet

GS4576C09L-33I

Manufacturer Part Number

GS4576C09L-33I

Description

144B UBGA - 5/6 RO

Manufacturer

GSI Technology

Datasheet

1.GS4576C09L-33I.pdf (63 pages)

Specifications of GS4576C09L-33I

Pack_quantity

126

Comm_code

85423239

Lead_time

Current page: 1 of 63
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144-Ball BGA

Commercial Temp

Industrial Temp

Features

• Pin- and function-compatible with Micron RLDRAM™ II

• 533 MHz DDR operation (1.067Gb/s/pin data rate)

• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock frequency)

• 16M x 36, 32M x 18, and 64M x 9 organizations available

• 8 banks

• Reduced cycle time (15 ns at 533 MHz)

• Address Multiplexing (Nonmultiplexed address option

• SRAM-type interface

• Programmable Read Latency (RL), row cycle time, and burst

• Balanced Read and Write Latencies in order to optimize data

• Data mask for Write commands

• Differential input clocks (CK, CK)

• Differential input data clocks (DKx, DKx)

• On-chip DLL generates CK edge-aligned data and output

• Data valid signal (QVLD)

• 32 ms refresh (16K refresh for each bank; 128K refresh

• 144-ball BGA package

• HSTL I/O (1.5 V or 1.8 V nominal)

• 25 –60 matched impedance outputs

• 2.5 V V

• On-die termination (ODT) R

• Commerical and Industrial Temperature

Rev: 1.01 4/2011

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

available)

sequence length

bus utilization

data clock signals

command must be issued in total each 32 ms)

Commercial (+0°

Industrial (–40°

EXT

, 1.8 V V

, 1.5 V or 1.8 V V

576Mb CIO Low Latency DRAM (LLDRAM

+95°C)

64M x 9, 32M x 18, 16M x 36

DDQ

I/O

1/63

Introduction

The GSI Technology 576Mb Low Latency DRAM

(LLDRAM™) II is a high speed memory device designed for

high address rate data processing typically found in networking

and telecommunications applications. The 8-bank architecture

and low tRC allows access rates formerly only found in

SRAMs.

The Double Data Rate (DDR) I/O interface provides high

bandwidth data transfers, clocking out two beats of data per

clock cycle at the I/O balls. Source-synchronous clocking can

be implemented on the host device with the provided free-

running data output clock.

Commands, addresses, and control signals are single data rate

signals clocked in by the True differential input clock

transition, while input data is clocked in on both crossings of

the input data clock(s).

Read and Write data transfers always in short bursts. The burst

length is programmable to 2, 4 or 8 by setting the Mode

The device is supplied with 2.5 V V

core, and 1.5 V or 1.8 V for the HSTL output drivers.

Internally generated row addresses facilitate bank-scheduled

refresh.

The device is delivered in an efficent BGA 144-ball package.

EXT

) II

GS4576C09/18/36L

and 1.8 V V

1.5 V or 1.8 V V

533 MHz–300 MHz

Preliminary

2.5 V V

1.8 V V

for the

DDQ

EXT

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