MC74HCT573ADWG ON Semiconductor, MC74HCT573ADWG Datasheet - Page 5

• Manufacturer Part Number: MC74HCT573ADWG
• Description: IC TXRX/LATCH OCTAL 3ST 20-SOIC
• Manufacturer: ON Semiconductor
• Series: 74HCTr
• Type: D-Typer

Specifications of MC74HCT573ADWG

• Logic Type: D-Type Transparent Latch
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 30ns
• Current - Output High, Low: 6mA, 6mA
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Number Of Circuits: 8
• Logic Family: 74HCT
• Polarity: Non-Inverting
• Input Bias Current (max): 4 uA
• High Level Output Current: - 6 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 30 ns at 5 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 55 C
• Mounting Style: SMD/SMT
• Rohs Compliant: YES
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Technology: CMOS
• Package Type: SOIC W
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 20
• Latch Type: Transparent
• Output Current: 6mA
• Propagation Delay: 28ns
• Ic Output Type: Tri State
• Supply Voltage Range: 4.5V To 5.5V
• Logic Case Style: SOIC
• No. Of Pins: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEVICE
UNDER
TEST
OUTPUT
ENABLE
INPUT D
Q
Q
Q
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
t
PLH
t
OUTPUT
r
DEVICE
UNDER
t
TLH
1.3 V
TEST
Figure 5. Test Circuit
Figure 6. Test Circuit
TEST POINT
10%
0.3 V
1.3 V
1.3 V
1.3 V
1.3 V
90%
2.7 V
t
t
PZL
PZH
Figure 1.
Figure 3.
C
1 kΩ
L
*
OUTPUT
t
t
PHZ
PLZ
TEST POINT
CONNECT TO V
TESTING t
CONNECT TO GND WHEN
TESTING t
t
C
f
L
*
SWITCHING WAVEFORMS
10%
90%
PLZ
PHZ
t
PHL
t
THL
AND t
AND t
http://onsemi.com
CC
3.0 V
GND
3.0 V
GND
HIGH
IMPEDANCE
V
V
HIGH
IMPEDANCE
WHEN
OL
OH
PZL
PZH
.
.
5
OUTPUT ENABLE
ENABLE
LATCH
INPUT D
ENABLE
LATCH ENABLE
LATCH
D0
D1
D2
D3
D4
D5
D6
D7
Q
2
3
4
5
6
7
8
9
1.3 V
EXPANDED LOGIC DIAGRAM
1.3 V
11
1
1.3 V
t
w
t
PLH
t
SU
Figure 2.
Figure 4.
VALID
1.3 V
t
PHL
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
D
LE
t
h
Q
Q
Q
Q
Q
Q
Q
Q
19
18
17
16
15
14
13
12
3.0 V
GND
3.0 V
GND
3.0 V
GND
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7