74ABT16841ADL,518 NXP Semiconductors, 74ABT16841ADL,518 Datasheet - Page 2

• Manufacturer Part Number: 74ABT16841ADL,518
• Description: IC 20BIT BUS INTFC LATCH 56SSOP
• Manufacturer: NXP Semiconductors
• Series: 74ABTr

Specifications of 74ABT16841ADL,518

• Logic Type: D-Type Transparent Latch
• Circuit: 10:10
• Output Type: Tri-State
• Voltage - Supply: 4.5 V ~ 5.5 V
• Independent Circuits: 2
• Delay Time - Propagation: 2.2ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74ABT16841ADL-T; 74ABT16841ADL-T; 935196770518

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
ORDERING INFORMATION
T
PIN DESCRIPTION
amb
Type number
74ABT16841ADL
74ABT16841ADGG
2004 Feb 02
High speed parallel latches
Live insertion/extraction permitted
Extra data width for wide address/data paths or buses carrying
parity
Power-up 3-State
Power-up reset
Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
Output capability: +64 mA / –32 mA
Latch-up protection exceeds 500 mA per Jedec Std 17
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
20-bit bus interface latch (3-State)
= –40 C to +85 C
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
SYMBOL
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
4, 11, 18, 25, 32, 39, 46, 53
C
t
t
I
I
C
CCZ
PLH
PHL
CCL
OUT
IN
PIN NUMBER
7, 22, 35, 50
56, 29
1, 28
Package
Name
SSOP56
TSSOP56
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Quiescent supply current
Quiescent supply current
Description
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
PARAMETER
1Q0 – 1Q9
2Q0 – 2Q9
1D0 – 1D9
2D0 – 2D9
1OE, 2OE
SYMBOL
1LE, 2LE
GND
V
CC
2
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is HIGH. This allows asynchronous operation,
as the output transition follows the data in transition. On the nLE
HIGH-to-LOW transition, the data that meets the set-up and hold
time is latched.
Data appears on the bus when the Output Enable (nOE) is LOW.
When nOE is HIGH the output is in the high-impedance state.
Outputs disabled; V
Data inputs
Data outputs
Output enable inputs (active-LOW)
Latch enable inputs (active rising edge)
Ground (0 V)
Positive supply voltage
Outputs LOW; V
T
V
amb
C
O
L
= 0 V or V
= 50 pF; V
V
CONDITIONS
= 25 C; GND = 0 V
I
= 0 V or V
CC
CC
CC
; 3-State
CC
CC
= 5 V
= 5.5 V
FUNCTION
= 5.5 V
74ABT16841A
TYPICAL
500
3.1
2.2
10
4
7
Version
SOT371-1
SOT364-1
Product data
UNIT
mA
pF
pF
ns
A