74LVT573PW,118 NXP Semiconductors, 74LVT573PW,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVT573PW,118
• Description: IC OCTAL D TRANSP LATCH 20TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr
• Type: D-Typer

Specifications of 74LVT573PW,118

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-TSSOP
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 2.7 V ~ 3.6 V
• Independent Circuits: 1
• Delay Time - Propagation: 6.3ns
• Current - Output High, Low: 32mA, 64mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 8
• Logic Family: LVT
• Polarity: Non-Inverting
• Input Bias Current (max): 3000 uA
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Propagation Delay Time: 2.7 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Number Of Elements: 1
• Latch Mode: Transparent
• Technology: BiCMOS
• Package Type: TSSOP
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVT573PW-T; 74LVT573PW-T; 935176360118

NXP Semiconductors
3. Ordering information
Table 1.
4. Functional diagram
74LVT573_4
Product data sheet
Type number
74LVT573D
74LVT573DB
74LVT573PW
74LVT573BQ
Fig 1.
Logic symbol
Ordering information
Package
Temperature range Name
40 C to +85 C
40 C to +85 C
40 C to +85 C
40 C to +85 C
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
OE
LE
11
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
mna807
19
18
17
16
15
14
13
12
SO20
SSOP20
TSSOP20
DHVQFN20
Rev. 04 — 15 September 2008
Description
plastic small outline package; 20 leads;
body width 7.5 mm
plastic shrink small outline package; 20 leads;
body width 5.3 mm
plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 20 terminals;
body 2.5
Fig 2.
4.5
3.3 V octal D-type transparent latch; (3-state)
IEC logic symbol
0.85 mm
11
2
3
4
5
6
7
8
9
1
1D
C1
EN1
mna808
74LVT573
19
18
17
16
15
14
13
12
© NXP B.V. 2008. All rights reserved.
Version
SOT163-1
SOT339-1
SOT360-1
SOT764-1
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