74LVT573D,118 NXP Semiconductors, 74LVT573D,118 Datasheet

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74LVT573D,118

Manufacturer Part Number
74LVT573D,118
Description
IC OCTAL D TRANSP LATCH 20SOIC
Manufacturer
NXP Semiconductors
Series
74LVTr
Datasheet

Specifications of 74LVT573D,118

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
6.3ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVT573D-T
74LVT573D-T
935170700118
1. General description
2. Features
The 74LVT573 is a high-performance BiCMOS product designed for V
3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The
two sections of the device are controlled independently by Latch Enable (LE) and Output
Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to
facilitate PC board layout and allow easy interface with microprocessors.
The data on the D inputs are transferred to the latch outputs when the Latch Enable (LE)
input is High. The latch remains transparent to the data inputs while LE is High, and stores
the data that is present one setup time before the High-to-Low enable transition.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS
memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all
eight 3-state buffers independent of the latch operation.
When OE is Low, the latched or transparent data appears at the outputs. When OE is
High, the outputs are in the High-impedance “OFF” state, which means they will neither
drive nor load the bus.
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74LVT573
3.3 V octal D-type transparent latch; (3-state)
Rev. 04 — 15 September 2008
Inputs and outputs arranged for easy interfacing to microprocessors
3-state outputs for bus interfacing
Common output enable control
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
No bus current loading when output is tied to 5 V bus
Power-up reset
Power-up 3-state
Latch-up protection
ESD protection:
Specified from 40 C to +85 C
N
N
N
JESD78 class II exceeds 500 mA
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Product data sheet
CC
operation at

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74LVT573D,118 Summary of contents

Page 1

V octal D-type transparent latch; (3-state) Rev. 04 — 15 September 2008 1. General description The 74LVT573 is a high-performance BiCMOS product designed for V 3.3 V. This device is an octal transparent latch coupled to eight 3-state ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name 74LVT573D +85 C 74LVT573DB +85 C 74LVT573PW +85 C 74LVT573BQ + Functional diagram Fig 1. Logic symbol 74LVT573_4 Product data sheet Description SO20 plastic small outline package; 20 leads; body width 7.5 mm SSOP20 plastic shrink small outline package; 20 leads; ...

Page 3

... NXP Semiconductors LATCH LATCH Fig 3. Logic diagram 5. Pinning information 5.1 Pinning 74LVT573 74LVTH573 GND 10 001aah713 Fig 4. Pin configuration for SO20, and (T)SSOP20 74LVT573_4 Product data sheet LATCH LATCH Fig 5. Rev. 04 — 15 September 2008 74LVT573 3.3 V octal D-type transparent latch; (3-state) ...

Page 4

... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin GND 19, 18, 17, 16, 15, 14, 13 Functional description 6.1 Function table [1] Table 3. Function table Operating mode Control OE Load and read register L enable Latch and read register L Hold L Disable outputs H [ HIGH voltage level LOW voltage level; ...

Page 5

... NXP Semiconductors Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter T storage temperature stg T junction temperature j P total power dissipation tot [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. ...

Page 6

... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter I input leakage current I I power-off leakage current OFF I bus hold LOW current BHL I bus hold HIGH current BHH I bus hold HIGH overdrive current BHHO I bus hold LOW overdrive current ...

Page 7

... NXP Semiconductors 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to ground (GND = 0 V); for test circuit see Symbol Parameter t LOW to HIGH PLH propagation delay t HIGH to LOW PHL propagation delay t OFF-state to HIGH PZH propagation delay t OFF-state to LOW PZL propagation delay t HIGH to OFF-state ...

Page 8

... NXP Semiconductors 11. Waveforms input PHL output Measurement points are given in Fig 6. Propagation delays latch enable input (LE) to output (Qn), and latch enable (LE) pulse width input PZH output Measurement points are given in V and V are typical voltage output levels that occur OL OH with the output load. ...

Page 9

... NXP Semiconductors Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance Test voltage for switching times. EXT Fig 11. Test circuitry for switching times Table 9. Test data Input 2.7 V ...

Page 10

... NXP Semiconductors 12. Package outline SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 11

... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 13. Package outline SOT339-1 (SSOP20) ...

Page 12

... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 13

... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 14

... Release date 74LVT573_4 20080915 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Section 3 “Ordering information” added. ...

Page 15

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 16

... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 4 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 13 Abbreviations ...

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