74LVT573MTC Fairchild Semiconductor, 74LVT573MTC Datasheet

IC LATCH TRANSP OCT 3ST 20TSSOP

74LVT573MTC

Manufacturer Part Number
74LVT573MTC
Description
IC LATCH TRANSP OCT 3ST 20TSSOP
Manufacturer
Fairchild Semiconductor
Series
74LVTr
Datasheets

Specifications of 74LVT573MTC

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.7 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
32mA, 64mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Number Of Circuits
8
Logic Family
74LVT
Polarity
Non-Inverting
High Level Output Current
- 32 mA
Low Level Output Current
64 mA
Propagation Delay Time
4.9 ns at 2.7 V, 4.4 ns at 3.3 V
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.7 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Current
5 mA
Latch Type
Transparent
Output Current
64mA
Propagation Delay
4.1ns
No. Of Bits
8
Ic Output Type
Tri State Non Inverted
Supply Voltage Range
2.7V To 3.6V
Logic Case Style
TSSOP
No. Of Pins
20
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
©1999 Fairchild Semiconductor Corporation
74LVT573, 74LVTH573 Rev. 1.7.0
74LVT573, 74LVTH573
Low Voltage Octal Transparent Latch with 3-STATE Outputs
Features
Ordering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Order Number
74LVT573WM
74LVT573SJ
74LVT573MSA
74LVT573MTC
74LVTH573WM
74LVTH573SJ
74LVTH573MSA
74LVTH573MTC
Input and output interface capability to systems at
5V V
Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs (74LVTH573),
also available without bushold feature (74LVT573)
Live insertion/extraction permitted
Power Up/Down high impedance provides glitch-free
bus loading
Outputs source/sink –32mA/+64mA
Functionally compatible with the 74 series 573
Latch-up performance exceeds 500mA
ESD performance:
– Human-body model
– Machine model
– Charged-device model
All packages are lead free per JEDEC: J-STD-020B standard.
CC
Package
Number
MSA20
MTC20
MSA20
MTC20
200V
M20D
M20D
M20B
M20B
2000V
1000V
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
General Description
The LVT573 and LVTH573 consist of eight latches
with 3-STATE outputs for bus organized system applica-
tions. The latches appear transparent to the data when
Latch Enable (LE) is HIGH. When LE is low, the data
satisfying the input timing requirements is latched. Data
appears on the bus when the Output Enable (OE) is
LOW. When OE is HIGH, the bus output is in the high
impedance state.
The LVTH573 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
These octal latches are designed for low-voltage (3.3V)
V
interface to a 5V environment. The LVT573 and
LVTH573 are fabricated with an advanced BiCMOS
technology to achieve high speed operation similar to 5V
ABT while maintaining a low power dissipation.
CC
Package Description
applications, but with the capability to provide a TTL
January 2008
www.fairchildsemi.com

Related parts for 74LVT573MTC

74LVT573MTC Summary of contents

Page 1

... Ordering Information Package Order Number Number 74LVT573WM M20B 74LVT573SJ M20D 74LVT573MSA MSA20 74LVT573MTC MTC20 74LVTH573WM M20B 74LVTH573SJ M20D 74LVTH573MSA MSA20 74LVTH573MTC MTC20 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard. ...

Page 2

... Enable (OE) input. When OE is LOW, the standard out- puts are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. ©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.0 Logic Symbols Truth Table LE ...

Page 3

... Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. ©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.0 3 www.fairchildsemi.com ...

Page 4

... Symbol V Supply Voltage CC V Input Voltage I I HIGH-Level Output Current OH I LOW-Level Output Current OL T Free-Air Operating Temperature Input Edge Rate, V ©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.0 Parameter (1) GND I GND Parameter 0.8V–2.0V Rating –0.5V to +4.6V – ...

Page 5

... An external driver must source at least the specified current to switch from LOW-to-HIGH external driver must sink at least the specified current to switch from HIGH-to-LOW. 6. This is the increase in supply current for each input that is at the specified voltage level rather than V ©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.0 V ...

Page 6

... The specification applies to any outputs switching in the same direction, either HIGH-to-LOW ( LOW-to-HIGH (t OSHL (11) Capacitance Symbol Parameter C Input Capacitance IN C Output Capacitance OUT Note: 11. Capacitance is measured at frequency f ©1999 Fairchild Semiconductor Corporation 74LVT573, 74LVTH573 Rev. 1.7.0 (7) Conditions V (V) C 50pF (8) 3.3 (8) 3 3.3V ± ...

Page 7

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 8

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 9

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 10

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifi ...

Page 11

... TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended exhaustive list of all such trademarks. ® ACEx Build it Now™ CorePLUS™ CROSSVOLT™ CTL™ Current Transfer Logic™ ...

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