74LV573N,112 NXP Semiconductors, 74LV573N,112 Datasheet - Page 9

• Manufacturer Part Number: 74LV573N,112
• Description: IC OCTAL D TRANSP LATCH 20-DIP
• Manufacturer: NXP Semiconductors
• Series: 74LVr

Specifications of 74LV573N,112

• Logic Type: D-Type Transparent Latch
• Package / Case: 20-DIP (0.300", 7.62mm)
• Circuit: 8:8
• Output Type: Tri-State
• Voltage - Supply: 1 V ~ 5.5 V
• Independent Circuits: 1
• Delay Time - Propagation: 24ns
• Current - Output High, Low: 16mA, 16mA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Through Hole
• Number Of Circuits: 8
• Logic Family: LV
• Polarity: Non-Inverting
• High Level Output Current: - 16 mA
• Low Level Output Current: 16 mA
• Propagation Delay Time: 12 ns at 3.3 V
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-2985-5; 935060100112

NXP Semiconductors
74LV573_3
Product data sheet
Fig 8.
Fig 9.
Measurement points are given in
V
Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays
Measurement points are given in
V
Enable and disable times
OL
OL
and V
and V
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Qn output
Qn output
OE input
Qn output
LE input
GND
V
V
GND
GND
V
V
OH
V
OL
V
Table
OH
Table
CC
OL
V
I
I
8.
8.
enabled
V
outputs
Rev. 03 — 15 April 2009
V
M
t
M
PLZ
t
t
PHZ
PHL
t
W
V
1/f
V
X
M
V
max
Y
disabled
outputs
t
t
Octal D-type transparent latch; 3-state
PLH
PZL
t
PZH
V
M
V
mna812
M
outputs
enabled
mna813
© NXP B.V. 2009. All rights reserved.
74LV573
9 of 18