AT91SAM7S128AU001 ATMEL Corporation, AT91SAM7S128AU001 Datasheet

AT91SAM7S128AU001

Manufacturer Part Number

AT91SAM7S128AU001

Description

QFP-64

Manufacturer

ATMEL Corporation

Datasheet

1.AT91SAM7S128AU001.pdf (600 pages)

Specifications of AT91SAM7S128AU001

Date_code

11+

Current page: 1 of 600
Download datasheet (7Mb)

Features

•

Incorporates the ARM7TDMI

Internal High-speed Flash

Internal High-speed SRAM, Single-cycle Access at Maximum Speed

Memory Controller (MC)

Reset Controller (RSTC)

Clock Generator (CKGR)

Power Management Controller (PMC)

Advanced Interrupt Controller (AIC)

Debug Unit (DBGU)

Periodic Interval Timer (PIT)

Windowed Watchdog (WDT)

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– EmbeddedICE

– 512 Kbytes (AT91SAM7S512) Organized in Two Contiguous Banks of 1024 Pages

– 256 kbytes(AT91SAM7S256) Organized in 1024 Pages of 256 Bytes (Single Plane)

– 128 Kbytes (AT91SAM7S128) Organized in 512 Pages of 256 Bytes (Single Plane)

– 64 Kbytes (AT91SAM7S64) Organized in 512 Pages of 128 Bytes (Single Plane)

– 32 Kbytes (AT91SAM7S321/32) Organized in 256 Pages of 128 Bytes (Single Plane)

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms

– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,

– Fast Flash Programming Interface for High Volume Production

– 64 kbytes (AT91SAM7S512/256)

– 32 kbytes (AT91SAM7S128)

– 16 kbytes (AT91SAM7S64)

– 8 kbytes (AT91SAM7S321/32)

– Embedded Flash Controller, Abort Status and Misalignment Detection

– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector

– Provides External Reset Signal Shaping and Reset Source Status

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to

– Three Programmable External Clock Signals

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two (AT91SAM7S512/256/128/64/321) or One (AT91SAM7S32) External Interrupt

– 2-wire UART and Support for Debug Communication Channel interrupt,

– 20-bit Programmable Counter plus 12-bit Interval Counter

– 12-bit key-protected Programmable Counter

– Provides Reset or Interrupt Signals to the System

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

of 256 Bytes (Dual Plane)

Flash Security Bit

500 Hz) and Idle Mode

Source(s) and One Fast Interrupt Source, Spurious Interrupt Protected

Programmable ICE Access Prevention

™

In-circuit Emulation, Debug Communication Channel Support

ARM

Thumb

Processor

AT91 ARM

Thumb-based

Microcontrollers

AT91SAM7S512

AT91SAM7S256

AT91SAM7S128

AT91SAM7S64

AT91SAM7S321

AT91SAM7S32

Preliminary

6175G–ATARM–22-Nov-06

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