EVAL-CONTROLBOARD AD [Analog Devices], EVAL-CONTROLBOARD Datasheet - Page 16

• Manufacturer Part Number: EVAL-CONTROLBOARD
• Description: 16-Bit, 100 kSPS CMOS ADC
• Manufacturer: AD [Analog Devices]

AD7660
which results in a longer BUSY width. In read-during-conversion
mode, the serial clock and data toggle at appropriate instants,
which minimizes potential feedthrough between digital activity
and the critical conversion decisions.
SLAVE SERIAL INTERFACE
External Clock
The AD7660 is configured to accept an externally supplied
serial data clock on the SCLK pin when the EXT/INT pin is
held high. In this mode, several methods can be used to read the
data. When CS and RD are both low, the data can be read after
each conversion or during the following conversion. The exter-
nal clock can be either a continuous or discontinuous clock. A
discontinuous clock can be either normally high or normally low
when inactive. Figure 18 and Figure 20 show the detailed timing
SDOUT
CS, RD
CNVST
SDOUT
CS, RD
CNVST
BUSY
SYNC
SCLK
BUSY
SYNC
SCLK
t
16
t
3
t
t
t
t
t
14
15
14
15
16
t
t
29
17
X
t
18
t
22
t
EXT/INT = 0
1
EXT/INT = 0
t
D15
3
t
1
20
X
t
t
22
19
t
21
t
20
D14
t
2
23
D15
1
t
t
19
18
RDC/SDIN = 1
RDC/SDIN = 0
3
D14
t
t
21
2
23
t
diagrams of these methods. Usually, because the AD7660 has a
longer acquisition phase than the conversion phase, the data are
read immediately after conversion.
While the AD7660 is performing a bit decision, it is important
that voltage transients not occur on digital input/output pins or
degradation of the conversion result could occur. This is particu-
larly important during the second half of the conversion phase
because the AD7660 provides error correction circuitry that can
correct for an improper bit decision made during the first half of
the conversion phase. For this reason, it is recommended that when
an external clock is being provided, it is a discontinuous clock
that is toggling only when BUSY is low or, more importantly,
that it does not transition during the latter half of BUSY high.
28
3
14
D2
INVSCLK = INVSYNC = 0
INVSCLK = INVSYNC = 0
14
D2
15
D1
15
D1
16
t
24
t
16
D0
30
t
24
D0
t
t
t
25
26
27
t
t
t
25
26
27