EVAL-CONTROLBOARD AD [Analog Devices], EVAL-CONTROLBOARD Datasheet - Page 11

• Manufacturer Part Number: EVAL-CONTROLBOARD
• Description: 16-Bit, 100 kSPS CMOS ADC
• Manufacturer: AD [Analog Devices]

CIRCUIT INFORMATION
The AD7660 is a fast, low-power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7660 is capable of
converting 100,000 samples per second (100 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 21 µW. This feature
makes the AD7660 ideal for battery-powered applications.
The AD7660 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7660 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in a
48-lead LQFP package that combines space savings and allows
flexible configurations as either serial or parallel interface. The
AD7660 is pin-to-pin-compatible with the AD7664.
CONVERTER OPERATION
The AD7660 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected
to a “dummy” capacitor of the same value as the capacitive
DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW
input IN. Thus, the capacitor array is used as a sampling capaci-
tor and acquires the analog signal on IN input. Similarly, the
“dummy” capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the CNVST input
goes or is low, a conversion phase is initiated. When the conver-
sion phase begins, SW
array and the “dummy” capacitor are then disconnected from
the inputs and connected to the REFGND input. Therefore, the
differential voltage between IN and INGND captured at the end
of the acquisition phase is applied to the comparator inputs, caus-
ing the comparator to become unbalanced.
By switching each element of the capacitor array between REFGND
or REF, the comparator input varies by binary weighted voltage
steps (V
these switches, starting with the MSB first, in order to bring the
comparator back into a balanced condition. After the comple-
tion of this process, the control logic generates the ADC output
code and brings BUSY output low.
A
REF
. All independent switches are connected to the analog
/2, V
REF
/4 . . . V
REFGND
A
INGND
and SW
REF
REF
IN
/65536). The control logic toggles
B
32768C
are opened first. The capacitor
16384C
MSB
4C
2C
67536C
C
Transfer Functions
Using the OB/2C digital input, the AD7660 offers two output
codings: straight binary and two’s complement. The LSB size is
V
teristic for the AD7660 is shown in Figure 4 and Table I.
Description
FSR – 1 LSB
FSR – 2 LSB
Midscale + 1 LSB 1.250038 V
Midscale
Midscale – 1 LSB
–FSR + 1 LSB
–FSR
NOTES
1
2
This is also the code for overrange analog input (V
This is also the code for underrange analog input (V
V
REF
REF
LSB
/65536, which is about 38.15 µV. The ideal transfer charac-
– V
C
Table I. Output Codes and Ideal Input Voltages
REFGND
111...111
111...110
111...101
000...010
000...001
000...000
LSB
).
SW
SW
0.5 LSB
0V
COMP
B
A
1.25 V
1 LSB = V
Analog
Input
2.499962 V
2.499923 V
1.249962 V
38 µV
0 V
1 LSB
SWITCHES
CONTROL
CONTROL
LOGIC
CNVST
REF
/65536
ANALOG INPUT
OUTPUT
CODE
BUSY
Straight
Binary
FFFF
FFFE
8001
8000
7FFF
0001
0000
Digital Output Code
V
REF
IN
2
IN
– V
–1.5 LSB
1
(Hexa)
below V
INGND
V
AD7660
REF
Two’s
Complement
7FFF
7FFE
0001
0000
FFFF
8001
8000
–1 LSB
above
INGND
2
1
).