EVAL-ADF9010EBZ AD [Analog Devices], EVAL-ADF9010EBZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-ADF9010EBZ
• Description: 900 MHz ISM Band Analog RF Front End
• Manufacturer: AD [Analog Devices]

Pin No.
17
19, 20
22, 23
25, 26
27, 28
30
31
32
33, 34
35, 36
38
39
40
41
42
43
45
47, 48
Mnemonic
V
LO
Tx
Tx
Tx
R
C
C
Rx
Rx
CE
S
S
S
MUXOUT
OVF
NC
Rx
CLK
DATA
LE
TUNE
SET
EXT
EXT
OUT
BB
BB
BB
BB
IN
EXT
4
3
QP, Rx
QN, Tx
IP, Tx
QN, Rx
IP, Rx
P, LO
P, Tx
BB
OUT
BB
EXT
IN
IN
BB
IN
BB
QN
N
QP
N
QP
Description
Control Input to the VCO. This input determines the VCO frequency and is derived from filtering the
CP output.
Single-Ended External VCO Input of 50 Ω. This is used if the ADF9010 utilizes an optional external VCO.
These pins are internally dc-biased and must be ac-coupled. AC-couple LO
and ac-couple the VCO signal with 100 pF through LO
Buffered Tx Output. These pins contain the Tx output signal, which can be combined in a balun for
best results.
Baseband Quadrature Phase Input/Complementary Input to the Transmit Modulator.
Baseband In-Phase Input/Complementary to the Transmit Modulator.
Connecting a resistor between this pin and AGND sets the maximum charge pump output current.
The nominal voltage potential at the R
where:
R
I
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled
to AGND with a value of 10 nF.
A capacitor connected to this pin is used to roll off noise from the VCO. It should be decoupled
to AGND with a value of 10 nF.
Output/Complementary Filtered Quadrature Signals from the Receive Filter Stage. The filtered
output is passed to the baseband MxFE chip.
Output/Complementary Filtered In-Phase from the Receive Filter Stage. The filtered output is
passed to the baseband MxFE chip.
Chip Enable. A Logic 0 on this pin powers down the device. A Logic 1 on this pin enables the device
depending on the status of the power-down bits.
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the S
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is
a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into
one of the four latches; the latch uses the control bits.
This multiplexer output allows either the PLL lock detect, the scaled VCO frequency, or the scaled
PLL reference frequency to be accessed externally.
A rising edge on this pin drops the gain of the Rx path by 6 dB. This is used to rapidly drop the gain
if the ADC detects an overload.
No Connect.
Input/Complementary Quadrature Input to the Receive Filter Stage.
CPMAX
SET
is 5.1 kΩ.
I
CPMAX
is 5 mA.
= 25.5/R
SET
Rev. 0 | Page 9 of 28
SET
pin is 0.66 V. The relationship between I
CLK
rising edge. This is a high impedance CMOS input.
EXT
P.
EXT
N to ground with 100 pF
CP
and R
ADF9010
SET
is