EVAL-ADF9010EBZ AD [Analog Devices], EVAL-ADF9010EBZ Datasheet - Page 14

• Manufacturer Part Number: EVAL-ADF9010EBZ
• Description: 900 MHz ISM Band Analog RF Front End
• Manufacturer: AD [Analog Devices]

ADF9010
LO Output
The LO
of an NPN differential pair driven by buffered outputs from the
VCO, as shown in Figure 18. To allow optimal power dissipation
vs. the output power requirements, the tail current of the diffe-
rential pair is programmable via Bit TP1 and Bit TP2 in the
control latch. The four current levels that can be set are: 6 mA,
8.5 mA, 11.5 mA, and 17.5 mA. These levels give output power
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,
if both outputs are combined in a 1 + 1:1 transformer or a 180°
microstrip coupler.
If the outputs are used individually, the optimum output stage
consists of a shunt inductor to V
Another feature of the ADF9010 is that the supply current to
the RF output stage is shut down until the part achieves lock as
measured by the digital lock detect circuitry. This is enabled by
the mute Tx until lock detect (F4) bit in the control latch.
Tx SECTION
Tx Baseband Inputs
Differential in-phase (I) and quadrature baseband (Q) inputs
are high impedance inputs that must be dc-biased to approx-
imately 500 mV dc and e driven from a low impedance source.
Nominal characterized ac signal swing is 700 mV p-p on each
pin. This results in a differential drive of 1.4 V p-p with a 500 mV
dc bias.
Tx
Tx
OUT
OUT
P
N
OUT
P and LO
VCO
Figure 18. LO Output Section
OUT
DIVIDE BY 4
BUFFER/
N pins are connected to the collectors
Figure 19. Tx Section
SPLITTER
PHASE
QUAD
DD
LO
.
OUT
Tx
Tx
TX BB IP
TX BB IN
P
INT/
EXT
BB
BB
QP
QN
VCO
LO
OUT
÷4
N
LO
LO
LO
LO
EXT
EXT
OUT
OUT
P
N
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N
P
Mixers
The ADF9010 has two double-balanced mixers, one for the
in-phase channel (I channel) and one for the quadrature
channel (Q channel). Both mixers are based on the Gilbert
cell design of four cross-connected transistors.
Tx Output
The Tx
to the collectors of four NPN differential pairs driven by the
baseband signals, as shown in Figure 20. To allow the user
optimal power dissipation vs. the output power requirements,
the tail current of the differential pair is programmable via
Bit TP1 and Bit TP2 in the control latch. Two levels can be set;
these levels give output power levels of −3 dBm and, +3 dBm,
respectively, using a 50 Ω resistor to V
50 Ω load. Alternatively, both outputs can be combined in a 1 +
1:1 transformer or a 180° microstrip coupler. This buffer can be
powered off if desired.
Another feature of the ADF9010 is that the supply current to the Tx
output stage is shut down until the part achieves lock as measured
by the digital lock detect circuitry. This is enabled by the mute LO
until lock detect bit (F5) in the control latch.
INTERFACING
Input Shift Register
The digital section of the ADF9010 includes a 24-bit input shift
register. Data is clocked into the 24-bit shift register on each
rising edge of S
transferred from the shift register to one of four latches on
the rising edge of S
the state of the two control bits (C2, C1) in the shift register.
These are the two LSBs, DB1 and DB0, as shown in Figure 21.
The truth table for Bit C3, Bit C2, and Bit C1 is shown in Table 7.
It displays a summary of how the latches are programmed. Note
that some bits are used for factory testing and should not be
programmed by the user.
Table 7. Truth Table
C3
X
0
1
X
X
LO
LO
IP
IN
OUT
Control Bits
P and Tx
C2
0
0
0
1
1
IP
CLK
. The data is clocked in MSB first. Data is
LE
OUT
. The destination latch is determined by
C1
0
1
0
1
1
N pins of the ADF9010 are connected
Figure 20. Tx Section
IN
Data Latch
Control latch
Tx latch
Rx calibration
LO latch
Rx filter
QP
DD
and ac coupling into a
QN
Tx
Tx
LO
LO
OUT
OUT
QP
QN
P
N