EVAL-AD7400EB AD [Analog Devices], EVAL-AD7400EB Datasheet - Page 4

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EVAL-AD7400EB

Manufacturer Part Number
EVAL-AD7400EB
Description
Isolated Sigma-Delta Modulator
Manufacturer
AD [Analog Devices]
Datasheet
AD7400
TIMING SPECIFICATIONS
V
Table 2.
Parameter
f
t
t
t
t
1
2
3
MCLKOUT
1
2
3
4
Sample tested during initial release to ensure compliance.
Mark space ratio for clock output is 40/60 to 60/40.
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.0 V.
3
DD1
3
= 4.5 V to 5.25 V, V
2
Limit at T
10
9/11
40
10
0.4 × t
0.4 × t
DD2
MCLKOUT
MCLKOUT
= 3 V to 5.5 V, T
MIN
MCLKOUT
, T
MDAT
MAX
Figure 2. Load Circuit for Digital Output Timing Specifications
A
= T
TO OUTPUT
Unit
MHz typ
MHz min/MHz max
ns max
ns min
ns min
ns min
MAX
to T
PIN
MIN
25pF
t
1
Figure 3. Data Timing
C
, unless otherwise noted.
Rev. A | Page 4 of 20
L
200µA
200µA
I
I
OL
OH
t
2
Description
Master clock output frequency
Master clock output frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
Master clock high time
+1.6V
t
3
1
t
4

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