EVAL-AD7400EB AD [Analog Devices], EVAL-AD7400EB Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD7400EB
• Description: Isolated Sigma-Delta Modulator
• Manufacturer: AD [Analog Devices]

AD7400
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 23. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKOUT cycle
and settle to the required accuracy within the next half cycle.
Since the AD7400 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role in
attaining the high performance available from the AD7400.
When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7400. The external capacitor at each input aids in supplying
the current spikes created during the sampling process, and the
resistor isolates the op amp from the transient nature of the load.
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure 24. A
capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
V
V
Figure 23. Analog Input Equivalent Circuit
IN
IN
Figure 24. Differential Input RC Network
V
V
+
–
IN
IN
+
–
MCLKOUT
1kΩ
1kΩ
R
R
φA
φB
φA
φB
C
φA
φB
AD7400
φA
φB
2pF
2pF
Rev. A | Page 14 of 20
DIGITAL FILTER
A Sinc
filter can be implemented on an FPGA or a DSP. The following
Verilog code provides an example of a Sinc
on a Xilinx® Spartan-II 2.5 V FPGA. This code can possibly be
compiled for another FPGA, such as an Altera® device. Note
that the data is read on the negative clock edge in this case;
although, it can be read on the positive edge, if preferred. Figure 28
shows the effect of using different decimation rates with various
filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
input
input
filtered*/
output [15:0] DATA;
integer location;
integer info_file;
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
reg word_clk;
reg init;
3
filter is recommended for use with the AD7400. This
mclk1;
reset;
mdata1;
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
ip_data1;
acc1;
acc2;
acc3;
acc3_d1;
acc3_d2;
diff1;
diff2;
diff3;
diff1_d;
diff2_d;
DATA;
word_count;
/*filtered op*/
3
filter implementation