EVAL-AD7324CB AD [Analog Devices], EVAL-AD7324CB Datasheet - Page 18

• Manufacturer Part Number: EVAL-AD7324CB
• Description: 4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

AD7324
Care should be taken to ensure that the analog input does not
exceed the V
Exceeding this value causes the diodes to become forward
biased and to start conducting into either the V
V
causing irreversible damage to the part.
In
can primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of the input
multiplexer and the track-and-hold switch. Capacitor C2 is the
sampling capacitor; its capacitance varies depending on the
analog input range selected (see the Specifications section).
Track-and-Hold Section
The track-and-hold on the analog input of the AD7324 allows
the ADC to accurately convert an input sine wave of full-scale
amplitude to 13-bit accuracy. The input bandwidth of the track-
and-hold is greater than the Nyquist rate of the ADC. The
AD7324 can handle frequencies up to 22 MHz.
The track-and-hold enters its tracking mode on the 14
rising edge after the CS falling edge. The time required to
acquire an input signal depends on how quickly the sampling
capacitor is charged. With 0 source impedance, 305 ns is
sufficient to acquire the signal to the 13-bit level. The
acquisition time required is calculated using the following
formula:
where C is the sampling capacitance and R is the resistance seen
by the track-and-hold amplifier looking back on the input. For
the AD7324, the value of R includes the on resistance of the
input multiplexer and is typically 300 Ω. R
any extra source impedance on the analog input.
SS
Figure 29 and Figure 30
supply rail. These diodes can conduct up to 10 mA without
t
ACQ
= 10 × ((R
Figure 30. Equivalent Analog Input Circuit (Differential)
V
V
IN
IN
DD
+
–
and V
SOURCE
SS
C1
C1
supply rails by more than 300 mV.
+ R) C)
V
V
, Capacitor C1 is typically 4 pF and
V
V
DD
DD
SS
SS
D
D
D
D
SOURCE
R1
R1
DD
should include
C2
C2
supply rail or
th
SCLK
Rev. 0 | Page 18 of 36
The AD7324 enters track mode on the 14
When running the AD7324 at a throughput rate of 1 MSPS with
a 20 MHz SCLK signal, the ADC has approximately
to acquire the analog input signal. The ADC goes back into
hold mode on the CS falling edge.
As the V
the input multiplexer increases. Therefore, based on the
equation for t
acquisition time provided to the AD7324 and, hence, decrease
the overall throughput rate.
throughput rate is reduced when operating with minimum V
and V
Unlike other bipolar ADCs, the AD7324 does not have a
resistive analog input structure. On the AD7324, the bipolar
analog signal is sampled directly onto the sampling capacitor.
This gives the AD7324 high analog input impedance. An
approximation for the analog input impedance can be
calculated from the following formula:
where f
capacitor value.
C
Specifications section). When operating at 1 MSPS, the analog
input impedance is typically 75 kΩ for the ±10V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases the
current required to drive the analog input therefore decreases.
S
depends on the analog input range chosen (see the
1.5 SCLK + t8 + t
Z = 1/(f
Figure 31. THD vs. ±V
SS
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
S
supplies, the specified THD performance is maintained.
DD
is the sampling frequency, and C
5
/V
1MSPS
S
SS
ACQ
× C
supply voltage is reduced, the on resistance of
, it is necessary to increase the amount of
7
S
)
750kSPS
QUIET
DD
9
/V
±V
SS
DD
and 1 MSPS
Supply Voltage at 500 kSPS, 750 kSPS,
Figure 31 shows that if the
/V
11
SS
SUPPLIES (V)
13
V
INTERNAL REFERENCE
T
F
±5V RANGE
SE MODE
A
IN
CC
S
th
= 25°C
= 10kHz
= V
is the sampling
SCLK rising edge.
15
DRIVE
500kSPS
= 5V
17
1
9
DD